From ab92f26a13f4656821f9dff93f180cb1a33c1c3e Mon Sep 17 00:00:00 2001 From: Ronak Kanabar Date: Mon, 28 Jan 2019 13:32:31 +0530 Subject: mainboard/{google,intel}: Remove SaGv hard coding Remove hard coding for SaGv config in devicetree.cb and apply macro for SaGv config for CNL variants boards Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Signed-off-by: Ronak Kanabar Reviewed-on: https://review.coreboot.org/c/31120 Tested-by: build bot (Jenkins) Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Subrata Banik --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 +- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 +- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 2 +- src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 2 +- src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb | 2 +- src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb | 2 +- src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb | 2 +- src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index f9d458208d..4efaf55191 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/cannonlake register "gen3_dec" = "0x000c0951" # 0x950-0x95f # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 0bf7e984a6..85d4f9def9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -14,7 +14,7 @@ chip soc/intel/cannonlake register "gen3_dec" = "0x000c0951" # 0x950-0x95f # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index bb963c9523..9604210794 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_FixedHigh" register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 55afde2cae..e2ebaba1cb 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_FixedHigh" register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 35aa624481..9648ac345b 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb index bbfc9e7913..126cab01f0 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb index bb963c9523..e5f867cbdc 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 010ad65103..e30da3af4d 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -5,7 +5,7 @@ chip soc/intel/cannonlake end # FSP configuration - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1" -- cgit v1.2.3