From aceaa71531e39042d98c6029313fc7d49a4c1d2b Mon Sep 17 00:00:00 2001 From: David Wu Date: Thu, 13 Sep 2018 16:51:14 +0800 Subject: mb/google/fizz: Provide baseboard and variant concepts In order to be able to share code across different fizz variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/fizz - code variants/fizz/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot CQ-DEPEND=CL:1273514 Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2 Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/28962 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/mainboard/google/fizz/Kconfig | 8 + src/mainboard/google/fizz/Makefile.inc | 6 + src/mainboard/google/fizz/acpi/dptf.asl | 72 --- src/mainboard/google/fizz/bootblock.c | 2 +- src/mainboard/google/fizz/chromeos.c | 2 +- src/mainboard/google/fizz/data.vbt | Bin 4608 -> 0 bytes src/mainboard/google/fizz/devicetree.cb | 488 --------------------- src/mainboard/google/fizz/dsdt.asl | 6 +- src/mainboard/google/fizz/ec.c | 2 +- src/mainboard/google/fizz/ec.h | 69 --- src/mainboard/google/fizz/gpio.h | 286 ------------ src/mainboard/google/fizz/mainboard.c | 2 +- src/mainboard/google/fizz/ramstage.c | 3 +- src/mainboard/google/fizz/smihandler.c | 2 +- .../google/fizz/variants/baseboard/devicetree.cb | 488 +++++++++++++++++++++ .../baseboard/include/baseboard/acpi/dptf.asl | 72 +++ .../fizz/variants/baseboard/include/baseboard/ec.h | 69 +++ .../variants/baseboard/include/baseboard/gpio.h | 286 ++++++++++++ src/mainboard/google/fizz/variants/fizz/data.vbt | Bin 0 -> 4608 bytes .../variants/fizz/include/variant/acpi/dptf.asl | 16 + .../google/fizz/variants/fizz/include/variant/ec.h | 21 + .../fizz/variants/fizz/include/variant/gpio.h | 21 + 22 files changed, 996 insertions(+), 925 deletions(-) delete mode 100644 src/mainboard/google/fizz/acpi/dptf.asl delete mode 100644 src/mainboard/google/fizz/data.vbt delete mode 100644 src/mainboard/google/fizz/devicetree.cb delete mode 100644 src/mainboard/google/fizz/ec.h delete mode 100644 src/mainboard/google/fizz/gpio.h create mode 100644 src/mainboard/google/fizz/variants/baseboard/devicetree.cb create mode 100644 src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl create mode 100644 src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h create mode 100644 src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h create mode 100644 src/mainboard/google/fizz/variants/fizz/data.vbt create mode 100644 src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/fizz/variants/fizz/include/variant/ec.h create mode 100644 src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 7f4989bf72..6ab94c910d 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -25,6 +25,10 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ if BOARD_GOOGLE_BASEBOARD_FIZZ +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_EC_EFS @@ -68,6 +72,10 @@ config TPM_TIS_ACPI_INTERRUPT int default 64 # GPE0_DW2_00 (GPP_E0) +config VARIANT_DIR + string + default "fizz" if BOARD_GOOGLE_FIZZ + config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_RT5663 diff --git a/src/mainboard/google/fizz/Makefile.inc b/src/mainboard/google/fizz/Makefile.inc index 534968cbf5..59f84b543a 100644 --- a/src/mainboard/google/fizz/Makefile.inc +++ b/src/mainboard/google/fizz/Makefile.inc @@ -26,3 +26,9 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl deleted file mode 100644 index f877c71c03..0000000000 --- a/src/mainboard/google/fizz/acpi/dptf.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define DPTF_CPU_PASSIVE 93 -#define DPTF_CPU_CRITICAL 100 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 77 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 70 -#define DPTF_TSR0_CRITICAL 83 -#define DPTF_TSR0_ACTIVE_AC0 95 -#define DPTF_TSR0_ACTIVE_AC1 85 -#define DPTF_TSR0_ACTIVE_AC2 60 -#define DPTF_TSR0_ACTIVE_AC3 52 -#define DPTF_TSR0_ACTIVE_AC4 44 -#define DPTF_TSR0_ACTIVE_AC5 38 -#define DPTF_TSR0_ACTIVE_AC6 35 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR1_PASSIVE 67 -#define DPTF_TSR1_CRITICAL 73 - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 44000, /* PowerLimitMinimum */ - 44000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) - -/* Include DPTF */ -#include diff --git a/src/mainboard/google/fizz/bootblock.c b/src/mainboard/google/fizz/bootblock.c index dc5dde1e50..4114cd55c7 100644 --- a/src/mainboard/google/fizz/bootblock.c +++ b/src/mainboard/google/fizz/bootblock.c @@ -16,7 +16,7 @@ #include #include -#include "gpio.h" +#include static void early_config_gpio(void) { diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index e52ac72662..98bee6b0ad 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -18,7 +18,7 @@ #include #include -#include "gpio.h" +#include #if ENV_RAMSTAGE #include diff --git a/src/mainboard/google/fizz/data.vbt b/src/mainboard/google/fizz/data.vbt deleted file mode 100644 index dbbf475f21..0000000000 Binary files a/src/mainboard/google/fizz/data.vbt and /dev/null differ diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb deleted file mode 100644 index 281d65ce87..0000000000 --- a/src/mainboard/google/fizz/devicetree.cb +++ /dev/null @@ -1,488 +0,0 @@ -chip soc/intel/skylake - - # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" - - # Mapping of USB port # to device - #+----------------+-------+-----------------------------------+ - #| Device | Port# | Rev | - #+----------------+-------+-----------------------------------+ - #| USB C | 1 | 2/3 | - #| USB A Rear | 2 | 2/3 | - #| USB A Front | 3 | 2/3 | - #| USB A Front | 4 | 2/3 | - #| USB A Rear | 5 | 2 on base celeron, 2/3 all others | - #| USB A Rear | 6 | 2 on base celeron, 2/3 all others | - #| Bluetooth | 7 | | - #| Daughter Board | 8 | | - #+----------------+-------+-----------------------------------+ - - # Bitmap for Wake Enable on USB attach/detach - register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(4) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - # Enable DPTF - register "dptf_enable" = "1" - - # Enable S0ix - register "s0ix_enable" = "1" - - # FSP Configuration - register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPwrOptEnable" = "1" - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" - register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" - register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" - register "PttSwitch" = "0" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "1" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" - register "SendVrMbxCmd" = "1" # IMVP8 workaround - register "VmxEnable" = "1" - - # Intersil VR c-state issue workaround - # send VR mailbox command for IA/GT/SA rails - register "IslVrCmd" = "2" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # VR Settings Configuration for 4 Domains - #+----------------+-------+-------+-------+-------+ - #| Domain/Setting | SA | IA | GTUS | GTS | - #+----------------+-------+-------+-------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | - #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | - #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | - #+----------------+-------+-------+-------+-------+ - #Note: IccMax settings are moved to SoC code - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 1030, - .dc_loadline = 1030, - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 240, - .dc_loadline = 240, - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, - .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), - .psi3threshold = VR_CFG_AMP(1), - .psi3enable = 1, - .psi4enable = 1, - .imon_slope = 0x0, - .imon_offset = 0x0, - .voltage_limit = 1520, - .ac_loadline = 310, - .dc_loadline = 310, - }" - - # Enable Root port 3(x1) for LAN. - register "PcieRpEnable[2]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[2]" = "1" - # RP 3 uses SRCCLKREQ0# - register "PcieRpClkReqNumber[2]" = "0" - # RP 3, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[2]" = "1" - # RP 3, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[2]" = "1" - # RP 3 uses uses CLK SRC 0 - register "PcieRpClkSrcNumber[2]" = "0" - - # Enable Root port 4(x1) for WLAN. - register "PcieRpEnable[3]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[3]" = "1" - # RP 4 uses SRCCLKREQ5# - register "PcieRpClkReqNumber[3]" = "5" - # RP 4, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[3]" = "1" - # RP 4, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[3]" = "1" - # RP 4 uses uses CLK SRC 5 - register "PcieRpClkSrcNumber[3]" = "5" - - # Enable Root port 5(x4) for NVMe. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # RP 5 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[4]" = "1" - # RP 5, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # RP 5, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # RP 5 uses CLK SRC 1 - register "PcieRpClkSrcNumber[4]" = "1" - - # Enable Root port 9 for BtoB. - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[8]" = "1" - # RP 9 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[8]" = "2" - # RP 9, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" - # RP 9, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[8]" = "1" - # RP 9 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[8]" = "2" - - # Enable Root port 11 for BtoB. - register "PcieRpEnable[10]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[10]" = "1" - # RP 11 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[10]" = "2" - # RP 11, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[10]" = "1" - # RP 11, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[10]" = "1" - # RP 11 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[10]" = "2" - - # Enable Root port 12 for BtoB. - register "PcieRpEnable[11]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[11]" = "1" - # RP 12 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[11]" = "2" - # RP 12, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[11]" = "1" - # RP 12, Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[11]" = "1" - # RP 12 uses uses CLK SRC 2 - register "PcieRpClkSrcNumber[11]" = "2" - - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug - register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear - - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC - register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM - register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug - register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C5 | Audio | - #+-------------------+---------------------------+ - - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 194, - .scl_hcnt = 100, - .sda_hold = 36, - }, - }, - }" - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSpi0] = PchSerialIoPci, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoSkipInit, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" - - register "speed_shift_enable" = "1" - register "tdp_psyspl2" = "90" - register "psys_pmax" = "120" - register "tcc_offset" = "6" # TCC of 94C - - # Use default SD card detect GPIO configuration - register "sdcard_cd_gpio_default" = "GPP_A7" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" - register "type" = "UPC_TYPE_A" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" - register "type" = "UPC_TYPE_A" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""10EC5663"" - register "name" = ""RT53"" - register "desc" = ""Realtek RT5663"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" - device i2c 13 on end - end - end # I2C #5 - device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP - device pci 1c.2 on - chip drivers/net - register "customized_leds" = "0x0fa5" - register "wake" = "GPE0_PCI_EXP" - register "device_index" = "1" - device pci 00.0 on end - end - end # PCI Express Port 3 - device pci 1c.3 on - chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" - device pci 00.0 on end - end - end # PCI Express Port 4 for WLAN - device pci 1c.4 on end # PCI Express Port 5 for NVMe - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 for 2nd LAN - chip drivers/net - register "customized_leds" = "0x0fa5" - register "device_index" = "2" - device pci 00.0 on end - end - end # PCI Express Port 9 for BtoB - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" - device spi 0 on end - end - end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index dc2fcfa321..8a35197608 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#include "ec.h" -#include "gpio.h" +#include +#include DefinitionBlock( "dsdt.aml", @@ -61,7 +61,7 @@ DefinitionBlock( Scope (\_SB) { /* Dynamic Platform Thermal Framework */ - #include "acpi/dptf.asl" + #include } /* USB port entries */ diff --git a/src/mainboard/google/fizz/ec.c b/src/mainboard/google/fizz/ec.c index 6b3ec9e35f..63a32a8c72 100644 --- a/src/mainboard/google/fizz/ec.c +++ b/src/mainboard/google/fizz/ec.c @@ -16,7 +16,7 @@ #include #include -#include "ec.h" +#include void mainboard_ec_init(void) { diff --git a/src/mainboard/google/fizz/ec.h b/src/mainboard/google/fizz/ec.h deleted file mode 100644 index 4b4044523f..0000000000 --- a/src/mainboard/google/fizz/ec.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_EC_H__ -#define __MAINBOARD_EC_H__ - -#include -#include - -#include "gpio.h" - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* - * EC can wake from S3 with lid or power button or key press or - * mode change event. - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Provide wake pin for EC */ -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ - -#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ - -#endif diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h deleted file mode 100644 index 9a94af4b1a..0000000000 --- a/src/mainboard/google/fizz/gpio.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef __MAINBOARD_GPIO_H__ -#define __MAINBOARD_GPIO_H__ - -#include -#include - -/* EC in RW */ -#define GPIO_EC_IN_RW GPP_C6 - -/* BIOS Flash Write Protect */ -#define GPIO_PCH_WP GPP_C23 - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* SKU_ID GPIOs */ -#define GPIO_SKU_ID0 GPP_C12 -#define GPIO_SKU_ID1 GPP_C13 -#define GPIO_SKU_ID2 GPP_C14 -#define GPIO_SKU_ID3 GPP_C15 - -/* OEM ID GPIOs */ -#define GPIO_OEM_ID1 GPP_D10 -#define GPIO_OEM_ID2 GPP_D11 -#define GPIO_OEM_ID3 GPP_D12 - -#ifndef __ACPI__ -/* Pad configuration in ramstage */ -/* Leave eSPI pins untouched from default settings */ -static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ -/* ESPI_IO0 */ -/* ESPI_IO1 */ -/* ESPI_IO2 */ -/* ESPI_IO3 */ -/* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ -/* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), -/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, - DEEP), /* eSPI mode */ -/* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ -/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), -/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ -/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), - -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, - NF1), /* CLK_PCIE_LAN_REQ# */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, - NF1), /* PCIE_CLKREQ_SSD# */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, - NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, - NF1), /* PCIE_CLKREQ_WLAN# */ -/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ -/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ -/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ -/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ -/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CS_L */ -/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CLK */ -/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MISO */ -/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, - DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, - DEEP), /* HWA_TRST_N */ -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ - -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, - DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, - DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, - DEEP), /* GPIO2 */ -/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, - DEEP), /* GPIO3 */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, - DEEP), /* GPIO4 */ -/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, - DEEP), /* SKU_ID0 */ -/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, - DEEP), /* SKU_ID1 */ -/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, - DEEP), /* SKU_ID2 */ -/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, - DEEP), /* SKU_ID3 */ -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, - DEEP), /* SCREW_SPI_WP_STATUS */ - -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, - PLTRST, EDGE), /* HP_IRQ_GPIO */ -/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, - DEEP), /* OEM_ID1 */ -/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, - DEEP), /* OEM_ID2 */ -/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, - DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ -/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ - -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, - NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, - NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ -/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, - NF1), /* Rear Dual-Stack USB Ports */ -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, - NF1), /* Front USB Ports */ -/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, - NF1), /* Rear Single USB Port */ -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, - NF1), /* INT_HDMI_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, - NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, - NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, - NF1), /* HDMI_DDCCLK_DATA */ -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), - -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ -/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SDA */ -/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, - NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), -/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ -/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, - NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), - -/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ -/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ - -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ -/* RSVD */ PAD_CFG_NC(GPD7), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { -/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CS_L */ -/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_CLK */ -/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MISO */ -/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, - NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ -/* Ensure UART pins are in native mode for H1. */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, - DEEP), /* SCREW_SPI_WP_STATUS */ -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, - NF1), /* MB_PCIE_SATA#_DET */ -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -}; - -#endif - -#endif diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 501510c457..9865f407e1 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/mainboard/google/fizz/ramstage.c b/src/mainboard/google/fizz/ramstage.c index 231ed87973..e208a678f6 100644 --- a/src/mainboard/google/fizz/ramstage.c +++ b/src/mainboard/google/fizz/ramstage.c @@ -18,12 +18,11 @@ #include #include #include -#include #include #include #include -#include "gpio.h" +#include #define GPIO_HDMI_HPD GPP_E13 #define GPIO_DP_HPD GPP_E14 diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c index 5f05b2e62c..3aa9ddb53a 100644 --- a/src/mainboard/google/fizz/smihandler.c +++ b/src/mainboard/google/fizz/smihandler.c @@ -17,7 +17,7 @@ #include #include -#include "ec.h" +#include void mainboard_smi_espi_handler(void) { diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..281d65ce87 --- /dev/null +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -0,0 +1,488 @@ +chip soc/intel/skylake + + # Deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + + # Mapping of USB port # to device + #+----------------+-------+-----------------------------------+ + #| Device | Port# | Rev | + #+----------------+-------+-----------------------------------+ + #| USB C | 1 | 2/3 | + #| USB A Rear | 2 | 2/3 | + #| USB A Front | 3 | 2/3 | + #| USB A Front | 4 | 2/3 | + #| USB A Rear | 5 | 2 on base celeron, 2/3 all others | + #| USB A Rear | 6 | 2 on base celeron, 2/3 all others | + #| Bluetooth | 7 | | + #| Daughter Board | 8 | | + #+----------------+-------+-----------------------------------+ + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable S0ix + register "s0ix_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPwrOptEnable" = "1" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "2" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + register "SendVrMbxCmd" = "1" # IMVP8 workaround + register "VmxEnable" = "1" + + # Intersil VR c-state issue workaround + # send VR mailbox command for IA/GT/SA rails + register "IslVrCmd" = "2" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m | + #+----------------+-------+-------+-------+-------+ + #Note: IccMax settings are moved to SoC code + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Enable Root port 3(x1) for LAN. + register "PcieRpEnable[2]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[2]" = "1" + # RP 3 uses SRCCLKREQ0# + register "PcieRpClkReqNumber[2]" = "0" + # RP 3, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[2]" = "1" + # RP 3, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[2]" = "1" + # RP 3 uses uses CLK SRC 0 + register "PcieRpClkSrcNumber[2]" = "0" + + # Enable Root port 4(x1) for WLAN. + register "PcieRpEnable[3]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[3]" = "1" + # RP 4 uses SRCCLKREQ5# + register "PcieRpClkReqNumber[3]" = "5" + # RP 4, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[3]" = "1" + # RP 4, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[3]" = "1" + # RP 4 uses uses CLK SRC 5 + register "PcieRpClkSrcNumber[3]" = "5" + + # Enable Root port 5(x4) for NVMe. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # RP 5 uses SRCCLKREQ1# + register "PcieRpClkReqNumber[4]" = "1" + # RP 5, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # RP 5, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # RP 5 uses CLK SRC 1 + register "PcieRpClkSrcNumber[4]" = "1" + + # Enable Root port 9 for BtoB. + register "PcieRpEnable[8]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[8]" = "1" + # RP 9 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[8]" = "2" + # RP 9, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[8]" = "1" + # RP 9, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[8]" = "2" + + # Enable Root port 11 for BtoB. + register "PcieRpEnable[10]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[10]" = "1" + # RP 11 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[10]" = "2" + # RP 11, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[10]" = "1" + # RP 11, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[10]" = "1" + # RP 11 uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[10]" = "2" + + # Enable Root port 12 for BtoB. + register "PcieRpEnable[11]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[11]" = "1" + # RP 12 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[11]" = "2" + # RP 12, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[11]" = "1" + # RP 12, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[11]" = "1" + # RP 12 uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[11]" = "2" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front + register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear + register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected) + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear + + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM + register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C5 | Audio | + #+-------------------+---------------------------+ + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 194, + .scl_hcnt = 100, + .sda_hold = 36, + }, + }, + }" + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + register "speed_shift_enable" = "1" + register "tdp_psyspl2" = "90" + register "psys_pmax" = "120" + register "tcc_offset" = "6" # TCC of 94C + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_A7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Left"" + register "type" = "UPC_TYPE_A" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right"" + register "type" = "UPC_TYPE_A" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left"" + register "type" = "UPC_TYPE_A" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Right"" + register "type" = "UPC_TYPE_A" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Middle"" + register "type" = "UPC_TYPE_A" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Left"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Right"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Middle"" + register "type" = "UPC_TYPE_USB3_A" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""10EC5663"" + register "name" = ""RT53"" + register "desc" = ""Realtek RT5663"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" + device i2c 13 on end + end + end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP + device pci 1c.2 on + chip drivers/net + register "customized_leds" = "0x0fa5" + register "wake" = "GPE0_PCI_EXP" + register "device_index" = "1" + device pci 00.0 on end + end + end # PCI Express Port 3 + device pci 1c.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_PCI_EXP" + device pci 00.0 on end + end + end # PCI Express Port 4 for WLAN + device pci 1c.4 on end # PCI Express Port 5 for NVMe + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 for 2nd LAN + chip drivers/net + register "customized_leds" = "0x0fa5" + register "device_index" = "2" + device pci 00.0 on end + end + end # PCI Express Port 9 for BtoB + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 0000000000..f877c71c03 --- /dev/null +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 93 +#define DPTF_CPU_CRITICAL 100 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 77 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 70 +#define DPTF_TSR0_CRITICAL 83 +#define DPTF_TSR0_ACTIVE_AC0 95 +#define DPTF_TSR0_ACTIVE_AC1 85 +#define DPTF_TSR0_ACTIVE_AC2 60 +#define DPTF_TSR0_ACTIVE_AC3 52 +#define DPTF_TSR0_ACTIVE_AC4 44 +#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_ACTIVE_AC6 35 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR1_PASSIVE 67 +#define DPTF_TSR1_CRITICAL 73 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 44000, /* PowerLimitMinimum */ + 44000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..a372f8dfb9 --- /dev/null +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include + +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Provide wake pin for EC */ +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */ + +#endif diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..05d9d038eb --- /dev/null +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* SKU_ID GPIOs */ +#define GPIO_SKU_ID0 GPP_C12 +#define GPIO_SKU_ID1 GPP_C13 +#define GPIO_SKU_ID2 GPP_C14 +#define GPIO_SKU_ID3 GPP_C15 + +/* OEM ID GPIOs */ +#define GPIO_OEM_ID1 GPP_D10 +#define GPIO_OEM_ID2 GPP_D11 +#define GPIO_OEM_ID3 GPP_D12 + +#ifndef __ACPI__ +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, + EDGE), /* SD_CDZ */ +/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ +/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, + DEEP), /* eSPI mode */ +/* ESPI_RESET# */ +/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ +/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, + NF1), /* CLK_PCIE_LAN_REQ# */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, + NF1), /* PCIE_CLKREQ_SSD# */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, + NF1), /* PCIE_CLKREQ_NGFF1# */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ +/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, + NF1), /* PCIE_CLKREQ_WLAN# */ +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, + DEEP), /* VR_DISABLE_L */ +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, + DEEP), /* HWA_TRST_N */ +/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ +/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SML0CLK */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, + DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, + DEEP), /* GPIO1 */ +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, + DEEP), /* GPIO2 */ +/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, + DEEP), /* GPIO3 */ +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, + DEEP), /* GPIO4 */ +/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, + DEEP), /* SKU_ID0 */ +/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, + DEEP), /* SKU_ID1 */ +/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, + DEEP), /* SKU_ID2 */ +/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, + DEEP), /* SKU_ID3 */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, + DEEP), /* SCREW_SPI_WP_STATUS */ + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ +/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ +/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), +/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, + PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, + DEEP), /* OEM_ID1 */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, + DEEP), /* OEM_ID2 */ +/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, + DEEP), /* OEM_ID3 */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ +/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ +/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ + +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, + NF1), /* DB_PCIE_SATA#_DET */ +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, + NF1), /* Rear Dual-Stack USB Ports */ +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, + NF1), /* Front USB Ports */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, + NF1), /* Rear Single USB Port */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, + NF1), /* INT_HDMI_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, + NF1), /* DDI2_HPD */ +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, + NF1), /* HDMI_DDCCLK_SW */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, + NF1), /* HDMI_DDCCLK_DATA */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), + +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, + NF1), /* PCH_I2C2_H1_3V3_SDA */ +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, + NF1), /* PCH_I2C2_H1_3V3_SCL */ +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), +/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, + NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, + NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ +/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), +/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), +/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), +/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), +/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), +/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), +/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), +/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), +/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), +/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), +/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ + +/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* H1_PCH_INT_ODL */ +/* Ensure UART pins are in native mode for H1. */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, + DEEP), /* SCREW_SPI_WP_STATUS */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ +}; + +#endif /* __ACPI__ */ + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/fizz/variants/fizz/data.vbt b/src/mainboard/google/fizz/variants/fizz/data.vbt new file mode 100644 index 0000000000..dbbf475f21 Binary files /dev/null and b/src/mainboard/google/fizz/variants/fizz/data.vbt differ diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..a9afa73115 --- /dev/null +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h b/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h new file mode 100644 index 0000000000..3d4fc8fa53 --- /dev/null +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h b/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h new file mode 100644 index 0000000000..cd34cf060a --- /dev/null +++ b/src/mainboard/google/fizz/variants/fizz/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +#endif /* __MAINBOARD_GPIO_H__ */ -- cgit v1.2.3