From bfe4a59bc97d086dc5152e5e082caaa09740aef6 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Wed, 13 Mar 2019 18:16:01 +0530 Subject: soc/intel/cannonlake: Pass coreboot debug interface info to FSP coreboot have an option to use legacy UART or LPSS UART. FSP will use the UART initialized by coreboot and we can choose an option to skip Uart initialization by FSP. For this, we need to pass correct debug interface flag to FSP through which FSP will know which UART port to use. If we don't pass correct interface information, FSP may try to dump logs on that port and it may slow down the system. BUG=none BRANCH=none TEST=Compile and boot with coreboot. Check FSP and coreboot logs are coming on serial port. Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/cannonlake/romstage/fsp_params.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 5597c4f230..791a6c83d3 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -48,6 +48,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; + /* + * PcdDebugInterfaceFlags + * This config will allow coreboot to pass information to the FSP + * regarding which debug interface is being used. + * Debug Interfaces: + * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub + * BIT2 - Not used. + */ + m_cfg->PcdDebugInterfaceFlags = + CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + /* Disable Vmx if Vt-d is already disabled */ if (config->VtdDisable) m_cfg->VmxEnable = 0; -- cgit v1.2.3