From c4772b9fd7fcc29d09d7617dc8cff922118814d7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 14 Apr 2019 18:38:35 +0200 Subject: cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset is common across multiple platforms. Therefore place it in a common location. Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32319 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Kyösti Mälkki Reviewed-by: Furquan Shaikh --- src/cpu/x86/early_reset.S | 45 +++++++++++++++++++++++ src/soc/intel/common/block/cpu/Makefile.inc | 1 + src/soc/intel/common/block/cpu/car/cache_as_ram.S | 17 +-------- 3 files changed, 48 insertions(+), 15 deletions(-) create mode 100644 src/cpu/x86/early_reset.S diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S new file mode 100644 index 0000000000..ec015abe22 --- /dev/null +++ b/src/cpu/x86/early_reset.S @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * input %esp: return address (not pointer to return address!) + * clobber the content of eax, ecx, edx + */ + +#include + +.section .text +.global check_mtrr + +check_mtrr: + /* Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. */ + +check_for_clean_reset: + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jnz warm_reset + jmp *%esp + /* perform warm reset */ +warm_reset: + movw $0xcf9, %dx + movb $0x06, %al + outb %al, %dx + /* Should not reach this*/ +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 5207227b49..a6c4f37cc4 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d3ee671bef..b1648e8eed 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -28,21 +28,8 @@ bootblock_pre_c_entry: post_code(0x20) - /* - * Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. - */ -check_for_clean_reset: - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax - cmp $0, %eax - jz no_reset - /* perform warm reset */ - movw $0xcf9, %dx - movb $0x06, %al - outb %al, %dx + movl $no_reset, %esp /* return address */ + jmp check_mtrr /* Check if CPU properly reset */ no_reset: post_code(0x21) -- cgit v1.2.3