From c48f5ef3cc623a4b1bccdbc9cb3e1d15505b7ad4 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sun, 11 Oct 2015 02:05:55 +0200 Subject: Kill lvds_num_lanes Only one value would work with corresponding gma code currently (which one depends on board). Going forward, it's possible to compute which number can be used, so there is no need to keep this info around. Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/11862 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/drivers/intel/gma/i915.h | 1 - src/mainboard/lenovo/t400/devicetree.cb | 1 - src/mainboard/lenovo/t420s/devicetree.cb | 1 - src/mainboard/lenovo/t430s/devicetree.cb | 1 - src/mainboard/lenovo/t520/devicetree.cb | 1 - src/mainboard/lenovo/t530/devicetree.cb | 1 - src/mainboard/lenovo/x200/devicetree.cb | 1 - src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/lenovo/x220/devicetree.cb | 1 - src/mainboard/lenovo/x230/devicetree.cb | 1 - src/mainboard/packardbell/ms2290/devicetree.cb | 1 - src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/nehalem/gma.c | 2 +- src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c | 2 +- src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c | 2 +- util/autoport/sandybridge.go | 5 ----- 16 files changed, 4 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h index ed6c23bca5..35f9c2596d 100644 --- a/src/drivers/intel/gma/i915.h +++ b/src/drivers/intel/gma/i915.h @@ -289,7 +289,6 @@ struct i915_gpu_controller_info { int use_spread_spectrum_clock; int link_frequency_270_mhz; - int lvds_num_lanes; u32 backlight; int ndid; u32 did[5]; diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index cf6157c963..af92d30e36 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -5,7 +5,6 @@ chip northbridge/intel/gm45 register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 9dd32c0e21..ca02455ff2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index e94fcb3993..7b83fbc8c8 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -14,7 +14,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index d23a6486b7..379a95d3af 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 1ead01cc0c..7db65c73ba 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 007141ca2e..36a1939369 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -5,7 +5,6 @@ chip northbridge/intel/gm45 register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 0a42a53478..0b53e22c67 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/nehalem register "gpu_pch_backlight" = "0x061a061a" register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "4" chip ec/lenovo/pmh7 device pnp ff.1 on # dummy diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 6e9054afcd..9c9ac7c175 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "4" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 25367c80f7..37d53d4492 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -15,7 +15,6 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "1" register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index 5ca123eb6c..54fd8ae221 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -39,7 +39,6 @@ chip northbridge/intel/nehalem register "gpu_pch_backlight" = "0x061a061a" register "gfx.use_spread_spectrum_clock" = "0" register "gfx.link_frequency_270_mhz" = "1" - register "gfx.lvds_num_lanes" = "4" device cpu_cluster 0 on chip cpu/intel/model_2065x diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 33eae84774..3dd051c924 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -244,7 +244,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); + / (link_frequency * 8 * 4); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index ed993f1270..c4e7731870 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -792,7 +792,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4)); + / (link_frequency * 8 * 4); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 7cb71f3713..c37959edde 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -313,7 +313,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock) - / (link_frequency * 8 * (info->lvds_num_lanes ? : 1)); + / (link_frequency * 8); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 9b2f1f2225..cd48174c0b 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -276,7 +276,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); + / (link_frequency * 8 * 4); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 227c111c8d..a2afc6cb37 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -16,13 +16,9 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { pchLVDS := inteltool.IGD[0xe1180] dualChannel := pchLVDS&(3<<2) == (3 << 2) pipe := (pchLVDS >> 30) & 1 - data_m1 := inteltool.IGD[0x60030+0x1000*pipe] & 0xffffff - data_n1 := inteltool.IGD[0x60034+0x1000*pipe] link_m1 := inteltool.IGD[0x60040+0x1000*pipe] link_n1 := inteltool.IGD[0x60044+0x1000*pipe] - data_factor := float32(data_m1) / float32(data_n1) link_factor := float32(link_m1) / float32(link_n1) - num_lanes := uint32((link_factor/data_factor)*18.0/8.0 + 0.5) fp0 := inteltool.IGD[0xc6040+8*pipe] dpll := inteltool.IGD[0xc6014+4*pipe] pixel_m2 := fp0 & 0xff @@ -54,7 +50,6 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), "gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0), - "gfx.lvds_num_lanes": FormatInt32(num_lanes), "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000), /* FIXME:XX hardcoded. */ "gfx.ndid": "3", -- cgit v1.2.3