From c56a558c18c7599d37a0f119b0a51c46cf274c32 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Sat, 8 Oct 2016 09:12:27 -0600 Subject: northbridge/amd: Modify 00670F00 chip.h to match DCT The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array. Original-Signed-off-by: Marshall Dawson Original-Reviewed-by: (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8) Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/17145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/amd/pi/00670F00/chip.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h index 917bc655ce..d11d7a405a 100644 --- a/src/northbridge/amd/pi/00670F00/chip.h +++ b/src/northbridge/amd/pi/00670F00/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +19,7 @@ struct northbridge_amd_pi_00670F00_config { - u8 spdAddrLookup[2][2][4]; + u8 spdAddrLookup[1][1][2]; }; #endif -- cgit v1.2.3