From c6313db34f26bcb8bdbb5ff04ebc9c9e7193cf0f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 16 Jan 2014 11:18:36 -0800 Subject: baytrail: Enable PCIe common clock and ASPM Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints. BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock: lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/182860 Reviewed-by: Aaron Durbin Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/5051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 9a3fa920be..a93b487b87 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -24,6 +24,8 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK select SMM_MODULES select SMM_TSEG select SMP -- cgit v1.2.3