From c82ab0adf568cab2e899e34715e1d07a37ff3ebe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 14 Oct 2015 16:03:56 +0300 Subject: pcengines/apu1: Fix SPD for 4GB model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Value of tRFCmin was incorrectly using 2 Gigabit chip data. There was no observed instability or bug reports because of this. Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/11899 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex index 4af1bf8fe7..876ee649a2 100644 --- a/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex +++ b/src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex @@ -127,7 +127,8 @@ # 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB # 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB # 0x500 = 160ns - for 2 Gigabit chips -00 05 +# 0x820 = 260ns - for 4 Gigabit chips +20 08 # 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) # 0x3c = 7.5 ns - All DDR3 SDRAM speed bins -- cgit v1.2.3