From cc1e3b64ed3621b06f853166bc767cc2625651d4 Mon Sep 17 00:00:00 2001 From: Matthias Gazzari Date: Sun, 29 Apr 2018 21:07:58 +0200 Subject: Fix freeze during chipset lockdown on Nehalem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c) and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue which became apparent with commit d533b16669a3bacb19b2824e6b4bc76a2a18c92a. More detailed, either setting the LSB of the 32 bit register at 0x98 of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the intel_model_2065x_finalize_smm function) indepentenly causes a freeze during bootup or a complete session loss on resuming from S3 as described here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register. Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series, Datasheet Volume Two" indicates that registers of the PCI device 00:00.0 cannot be locked manually. Instead, they can only be locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK. Finally, the addresses and sizes of these registers were partially wrong. Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT support compared to the Core i5 and Core i7 processors of a X201). Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b Signed-off-by: Matthias Gazzari Reviewed-on: https://review.coreboot.org/25914 Reviewed-by: Nicola Corna Reviewed-by: Jonathan Neuschäfer Reviewed-by: Kyösti Mälkki Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/model_2065x/finalize.c | 3 --- src/cpu/intel/model_2065x/model_2065x.h | 1 - src/northbridge/intel/nehalem/finalize.c | 12 ------------ 3 files changed, 16 deletions(-) diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 50e00bf74a..5e7b3d847c 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -54,7 +54,4 @@ void intel_model_2065x_finalize_smm(void) /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); - - /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 8bb3b877e8..f87ba77460 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -39,7 +39,6 @@ #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401 #define MSR_PIC_MSG_CONTROL 0x2e diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index f90f93769f..7313840606 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -23,18 +23,6 @@ void intel_nehalem_finalize_smm(void) { - pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ -- cgit v1.2.3