From d250063c09d432cff563331a3dfb158d7c6a7a46 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 21 Jan 2020 21:54:14 -0800 Subject: mb/intel/tglrvp: Enable SATA Enable both SATA ports for TGLRVP. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory Signed-off-by: Wonkyu Kim Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505 Reviewed-by: Nick Vaccaro Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index fbd1c39dce..01e0f3f8f8 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -45,6 +45,10 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -122,7 +126,7 @@ chip soc/intel/tigerlake device pci 16.3 off end # CSME 0xA0E3 device pci 16.4 off end # HECI3 0xA0E4 device pci 16.5 off end # HECI4 0xA0E5 - device pci 17.0 off end # SATA 0xA0D3 + device pci 17.0 on end # SATA 0xA0D3 device pci 19.0 off end # I2C4 0xA0C5 device pci 19.1 on end # I2C5 0xA0C6 device pci 19.2 on end # UART2 0xA0C7 -- cgit v1.2.3