From d694f6e21b4a24c70adb55b65f095bc87a9878cd Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Mon, 22 Apr 2019 09:41:14 -0700 Subject: mb/google/sarien: Add SMBIOS type 9 fields Fill SMBIOS type 9 fields for both sarien and arcada platform. BUG=b:129485789 TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry. Signed-off-by: Lijian Zhao Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 8 ++++++-- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 8 ++++++-- src/soc/intel/cannonlake/chip.h | 1 + 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 77bd82a64b..0cc9970488 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -349,11 +349,15 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e9786f14eb..3807047e0f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -378,11 +378,15 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 40d9f71eed..b17df4b21b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3