From d912f1d4f973f415a431932b71e9cee0b1c82549 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 15 Feb 2016 20:07:42 +0100 Subject: nb/intel/sandybridge/raminit: Adjust timB to prevent overflow Improved version of I1a115a45d5febf351d89721ece79eaf43f7ee8a0 The first version wasn't well tested due to the lack of hardware and it was to aggressive. With timC being direct function of timB's 6 LSBs it's critical to match timC and timB. Some tests increments the value of timB by a small value, which might cause the 6bit value to overflow, if it's close to 0x3F. Increment the value by a small offset if it's likely to overflow, to make sure it won't overflow while running tests and bricks the system due to a non matching timC. In comparission to the first attempt, only 4 out of 128 timB values are considered bad. Needs test on real hardware ! Fixes a "edge write discovery failed" on my test system. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/13714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/intel/sandybridge/raminit.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 40089e2cdb..b81860264d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -2381,6 +2381,19 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) } FOR_ALL_LANES { struct run rn = get_longest_zero_run(statistics[lane], 128); + /* timC is a direct function of timB's 6 LSBs. + * Some tests increments the value of timB by a small value, + * which might cause the 6bit value to overflow, if it's close + * to 0x3F. Increment the value by a small offset if it's likely + * to overflow, to make sure it won't overflow while running + * tests and bricks the system due to a non matching timC. + * + * TODO: find out why some tests (edge write discovery) + * increment timB. */ + if ((rn.start & 0x3F) == 0x3E) + rn.start += 2; + else if ((rn.start & 0x3F) == 0x3F) + rn.start += 1; ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; if (rn.all) die("timB discovery failed"); -- cgit v1.2.3