From dfecd2740b9ecc6950bf08b8b40573158541d56a Mon Sep 17 00:00:00 2001 From: Liu Tao Date: Sun, 17 Oct 2010 21:34:45 +0000 Subject: We currently read the CPU HT speed from HT chain 0's register. Fix that to read the register from the chain where the SB chip is on. Signed-off-by: Liu Tao Acked-by: Myles Watson Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/rs780/rs780_gfx.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index 7208acd864..1667775658 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -304,7 +304,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) volatile u32 * pointer; int i; u16 command; - u32 value; + u32 value, sblink; u16 deviceid, vendorid; device_t nb_dev = dev_find_slot(0, 0); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); @@ -453,9 +453,15 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.usMinNBVoltage = 0; vgainfo.usBootUpNBVoltage = 0x1a; + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + value = pci_read_config32(k8_f0, 0x64); + sblink = (value >> 8) & 0x3; + printk(BIOS_DEBUG, "SBLINK = %d.\n", sblink); + + /* HT speed */ value = pci_read_config32(nb_dev, 0xd0); printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); - value = pci_read_config32(k8_f0, 0x88); + value = pci_read_config32(k8_f0, 0x88 + (sblink * 0x20)); printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */ -- cgit v1.2.3