From e52592078e8e5b24b45197ab510236193656f68e Mon Sep 17 00:00:00 2001 From: Venkateswarlu Vinjamuri Date: Fri, 2 Sep 2016 16:07:08 -0700 Subject: mainboard/google/reef: Enable audio clock and power gate Removes S0ix blocker. Sets audio clock gate and power gate bits when audio not in use. Reduces power in S0. Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b Signed-off-by: Venkateswarlu Vinjamuri Reviewed-on: https://review.coreboot.org/16424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/reef/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 9a7c2d17b3..2ac20de2dc 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -38,6 +38,11 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route, i.e., if this route changes then the affected GPE -- cgit v1.2.3