From e56d734816490d4157f94b38331a4ce10fb38366 Mon Sep 17 00:00:00 2001 From: Pravin Angolkar Date: Wed, 22 Jul 2015 17:27:56 +0530 Subject: Kunimitsu: Enable root ports and clkreqs This patch enables the root ports and configures the clock req numbers as per the design On kunimitsu FAB3 board with D0 MCP Root port 1 --> Wifi card --> clkreq 1 Root port 4 --> Kepler VP8/VP9--> clkreq 2 BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for Kunimitsu and Boot Kunimitsu board with D0 MCP Original-Change-Id: I4e110d2d07efbfa7a306852301cd1cd89027b2ba Original-Signed-off-by: Pravin Angolkar Original-Reviewed-on: https://chromium-review.googlesource.com/290051 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Naveenkrishna Ch Original-Tested-by: Naveenkrishna Ch Change-Id: I6d66c78496ac3f43e07d96feefed35cf50da6aa1 Signed-off-by: Pravin Angolkar Reviewed-on: http://review.coreboot.org/11232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/intel/kunimitsu/devicetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 6f03bbf793..e414928e02 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -28,8 +28,15 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" + # Pcie RootPort + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + # GPE configuration register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 register "gpe0_en_2" = "0x00000010" register "gpe0_en_3" = "0x00000000" -- cgit v1.2.3