From e6e9fa6ef90bc62d645da942f3bdc7bdeb1c1930 Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Wed, 6 May 2020 09:18:37 +0200 Subject: soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip options Intel introduced the UPD VrPowerDeliveryDesign with Cannon Lake. The BIOS needs to program VrPowerDeliverDesign configuration per platform according to the platform capabilities to avoid incorrect electrial/power parameters. This is only added for Cannon Lake. Refer to document 599797 for more details. Change-Id: I89b8dceb40fa6a9dc67b218e91bf728ff928b5a0 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/41081 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 4 ++++ src/soc/intel/cannonlake/fsp_params.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 4f015a71f7..f6ec7ce7cb 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -413,6 +413,10 @@ struct soc_intel_cannonlake_config { uint8_t LanWakeFromDeepSx; uint8_t WolEnableOverride; +#if !CONFIG(SOC_INTEL_COMETLAKE) + uint32_t VrPowerDeliveryDesign; +#endif + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b432087a32..b7e9ad8d8b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -459,6 +459,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) #endif } +#if !CONFIG(SOC_INTEL_COMETLAKE) + params->VrPowerDeliveryDesign = config->VrPowerDeliveryDesign; +#endif + dev = pcidev_path_on_root(SA_DEVFN_IGD); if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled) params->PeiGraphicsPeimInit = 1; -- cgit v1.2.3