From eb86016570d0f7dde331d6df531f386bff590fb1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 20 Jun 2020 18:03:27 +0200 Subject: nb/intel/haswell: Use 16-bit ops on PCI COMMAND The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops to update it. Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Rudolph --- src/northbridge/intel/haswell/minihd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index c6b5a1257c..de2ce06410 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,7 +59,7 @@ static void minihd_init(struct device *dev) printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); -- cgit v1.2.3