From ed009371030cb97571c8b8dc342f16a9fa124d59 Mon Sep 17 00:00:00 2001 From: Eswar Nallusamy Date: Wed, 2 Nov 2005 17:32:49 +0000 Subject: ppc970 initial porting. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/ppc/Config.lb | 10 + src/arch/ppc/include/ppc970.h | 2019 +++++++-- src/arch/ppc/include/ppc970lib.h | 279 ++ src/arch/ppc/init/ldscript.lb | 460 ++- src/arch/ppc/init/ppc_main.c | 6 + src/arch/ppc/lib/c_start.S | 3 + src/arch/ppc/lib/div64.S | 5 + src/arch/ppc/lib/timebase.S | 18 + src/cpu/ppc/ppc970/Config.lb | 9 +- src/cpu/ppc/ppc970/clock.c | 27 + src/cpu/ppc/ppc970/ppc970.inc | 920 +++-- src/cpu/ppc/ppc970/ppc970excp.S | 11 + src/cpu/ppc/ppc970/ppc970lib.S | 5027 +++++++++++++++++++++++ src/mainboard/embeddedplanet/ep405pc/Options.lb | 1 + src/mainboard/momentum/apache/Config.lb | 109 +- src/mainboard/momentum/apache/boardutil.c | 406 ++ src/mainboard/momentum/apache/boardutil.h | 154 + src/mainboard/momentum/apache/init.c | 133 + src/mainboard/momentum/apache/mainboard.c | 12 + src/mainboard/momentum/apache/ppc970fx.h | 1191 ------ src/mainboard/momentum/apache/timerspeed.S | 378 ++ src/northbridge/ibm/cpc925/Config.lb | 2 + src/northbridge/ibm/cpc925/cpc925_sdram.c | 13 + 23 files changed, 9240 insertions(+), 1953 deletions(-) create mode 100755 src/arch/ppc/include/ppc970lib.h create mode 100644 src/cpu/ppc/ppc970/clock.c create mode 100755 src/cpu/ppc/ppc970/ppc970excp.S create mode 100755 src/cpu/ppc/ppc970/ppc970lib.S create mode 100644 src/mainboard/momentum/apache/boardutil.c create mode 100755 src/mainboard/momentum/apache/boardutil.h create mode 100644 src/mainboard/momentum/apache/init.c create mode 100644 src/mainboard/momentum/apache/mainboard.c delete mode 100644 src/mainboard/momentum/apache/ppc970fx.h create mode 100755 src/mainboard/momentum/apache/timerspeed.S create mode 100644 src/northbridge/ibm/cpc925/cpc925_sdram.c diff --git a/src/arch/ppc/Config.lb b/src/arch/ppc/Config.lb index 31ccc297ce..57931d2d89 100644 --- a/src/arch/ppc/Config.lb +++ b/src/arch/ppc/Config.lb @@ -5,6 +5,16 @@ makerule linuxbios.rom action "cp $< $@" end +makerule clean + action "rm -f linuxbios.* *~" + action "rm -f linuxbios" + action "rm -f ldscript.ld" + action "rm -f a.out *.s *.l *.o *.E *.inc" + action "rm -f TAGS tags romcc*" + action "rm -f docipl buildrom* chips.c *chip.c linuxbios_ram* linuxbios_pay*" + action "rm -f build_opt_tbl* nrv2b* option_table.c" +end + dir init dir lib dir boot diff --git a/src/arch/ppc/include/ppc970.h b/src/arch/ppc/include/ppc970.h index 5c0f884972..3117609b87 100644 --- a/src/arch/ppc/include/ppc970.h +++ b/src/arch/ppc/include/ppc970.h @@ -1,242 +1,1777 @@ -/*kernel/include/sys/as_archppc970.h, epos_code, epos_1.0 8/25/04 15:33:07*/ -/*----------------------------------------------------------------------------+ -| COPYRIGHT I B M CORPORATION 2003 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -| US Government Users Restricted Rights - Use, duplication or -| disclosure restricted by GSA ADP Schedule Contract with -| IBM Corp. -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| EPOS -| Author: Maciej P. Tyrlik -| Component: Include file. -| File: sys/as_archppc970.h -| Purpose: Assembler include file for PPC970 processor. -| Changes: -| Date: Comment: -| ----- -------- -| 13-Oct-03 Created MPT -+----------------------------------------------------------------------------*/ - -#ifndef _PPC970_H_ -#define _PPC970_H_ - -/*----------------------------------------------------------------------------+ -| When timers are running based on CPU speed this is the timer to CPU frequency -| ratio. -+----------------------------------------------------------------------------*/ -#define PPC970_TB_RATIO 8 - -/*----------------------------------------------------------------------------+ -| Cache line size. -+----------------------------------------------------------------------------*/ -#define CACHE_LINE_SIZE_L1 128 -#define CACHE_LINE_SIZE_L2 128 - -/*----------------------------------------------------------------------------+ -| SLB size. -+----------------------------------------------------------------------------*/ -#define SLB_SIZE 64 - -/*----------------------------------------------------------------------------+ -| TLB size. -+----------------------------------------------------------------------------*/ -#define TLB_SIZE 1024 - -/*----------------------------------------------------------------------------+ -| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64) -| sprg0 (64), sprg1 (64), sprg2 (64), sprg3 (64), pvr (32) tblr (64), tbur (32) -| registers are defined in as_archppc.h. -+----------------------------------------------------------------------------*/ -#define SPR_ACCR 0x001D /* 64-bit read/write $*/ -#define SPR_ASR 0x0118 /* 64-bit read/write, write hypervisor only */ -#define SPR_DABR 0x03F5 /* 64-bit read/write, write hypervisor only */ -#define SPR_DABRX 0x03F7 /* 64-bit read/write, write hypervisor only */ -#define SPR_DAR 0x0013 /* 64-bit read/write */ -#define SPR_DEC 0x0016 /* 32-bit read/write */ -#define SPR_DSISR 0x0012 /* 32-bit read/write */ -#define SPR_HDEC 0x0136 /* 64-bit read/write, write hypervisor only */ -#define SPR_HID0 0x03F0 /* 64-bit read/write, write hypervisor only */ -#define SPR_HID1 0x03F1 /* 64-bit read/write, write hypervisor only */ -#define SPR_HID4 0x03F4 /* 64-bit read/write, write hypervisor only */ -#define SPR_HID5 0x03F6 /* 64-bit read/write, write hypervisor only */ -#define SPR_HIOR 0x0137 /* 64-bit read/write */ -#define SPR_HSPRG0 0x0130 /* 64-bit read/write, write hypervisor only */ -#define SPR_HSPRG1 0x0131 /* 64-bit read/write, write hypervisor only */ -#define SPR_HSRR0 0x013A /* 64-bit read/write, write hypervisor only */ -#define SPR_HSRR1 0x013B /* 64-bit read/write, write hypervisor only */ -#define SPR_IMC 0x030F /* 64-bit read/write */ -#define SPR_MMCR0 0x031B /* 64-bit read/write */ -#define SPR_MMCR1 0x031E /* 64-bit read/write */ -#define SPR_MMCRA 0x0312 /* 64-bit read/write */ -#define SPR_PIR 0x03FF /* 32-bit read */ -#define SPR_PMC1 0x0313 /* 32-bit read/write */ -#define SPR_PMC2 0x0314 /* 32-bit read/write */ -#define SPR_PMC3 0x0315 /* 32-bit read/write */ -#define SPR_PMC4 0x0316 /* 32-bit read/write */ -#define SPR_PMC5 0x0317 /* 32-bit read/write */ -#define SPR_PMC6 0x0318 /* 32-bit read/write */ -#define SPR_PMC7 0x0319 /* 32-bit read/write */ -#define SPR_PMC8 0x031A /* 32-bit read/write */ -#define SPR_SCOMC 0x0114 /* 64-bit read/write, write hypervisor only */ -#define SPR_SCOMD 0x0115 /* 64-bit read/write, write hypervisor only */ -#define SPR_SDAR 0x031D /* 64-bit read/write */ -#define SPR_SDR1 0x0019 /* 64-bit read/write, write hypervisor only */ -#define SPR_SIAR 0x031C /* 64-bit read/write */ -#define SPR_TBL_WRITE 0x011C /* 32-bit write */ -#define SPR_TBU_WRITE 0x011D /* 32-bit write */ -#define SPR_TRACE 0x03FE /* 64-bit read $*/ -#define SPR_TRIG0 0x03D0 /* 64-bit write */ -#define SPR_TRIG1 0x03D1 /* 64-bit write */ -#define SPR_TRIG2 0x03D2 /* 64-bit write */ -#define SPR_VRSAVE 0x0100 /* 64-bit read/write $*/ - -/*----------------------------------------------------------------------------+ -| Vector status and control register is accessed using the mfvscr and mtvscr -| instructions. -+----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------+ -| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1, -| register bits are defined in as_archppc.h. This is a 64-bit register. -+----------------------------------------------------------------------------*/ -#define MSR_SF 0x8000000000000000 /* 64/32 bit mode indicator */ -#define MSR_HV 0x1000000000000000 /* hypervisor mode */ -#define MSR_VMX 0x0000000002000000 /* vmx unit available */ -#define MSR_POW 0x0000000000040000 /* power management enable */ -#define MSR_SE 0x0000000000000400 /* single step */ -#define MSR_BE 0x0000000000000200 /* branch trace */ -#define MSR_IS 0x0000000000000020 /* instruction address space */ -#define MSR_DS 0x0000000000000010 /* data address space */ -#define MSR_PM 0x0000000000000004 /* performance monitor */ -#define MSR_RI 0x0000000000000002 /* recoverable interrupt */ - -/*----------------------------------------------------------------------------+ -| HID0 bits. -+----------------------------------------------------------------------------*/ -#define HID0_ONEPPC 0x8000000000000000 -#define HID0_SINGLE 0x4000000000000000 -#define HID0_ISYNC_SC 0x2000000000000000 -#define HID0_SERIAL_G 0x1000000000000000 -#define HID0_DEEP_NAP 0x0100000000000000 -#define HID0_NAP 0x0040000000000000 -#define HID0_DPM 0x0010000000000000 -#define HID0_TR_GR 0x0004000000000000 -#define HID0_TR_DIS 0x0002000000000000 -#define HID0_NHR 0x0001000000000000 -#define HID0_INORDER 0x0000800000000000 -#define HID0_ENH_TR 0x0000400000000000 -#define HID0_TB_CTRL 0x0000200000000000 -#define HID0_EXT_TB_EN 0x0000100000000000 -#define HID0_CIABR_EN 0x0000020000000000 -#define HID0_HDEC_EN 0x0000010000000000 -#define HID0_EB_THERM 0x0000008000000000 -#define HID0_EN_ATTN 0x0000000100000000 -#define HID0_EN_MAC 0x0000000080000000 - -/*----------------------------------------------------------------------------+ -| HID1 bits. -+----------------------------------------------------------------------------*/ -#define HID1_BHT_PM 0xE000000000000000 -#define HID1_BHT_STATIC 0x0000000000000000 -#define HID1_BHT_GLOBAL 0x4000000000000000 -#define HID1_BHT_LOCAL 0x8000000000000000 -#define HID1_BHT_GL_LO 0xC000000000000000 -#define HID1_BHT_GL_CO 0x6000000000000000 -#define HID1_BHT_FULL 0xE000000000000000 -#define HID1_EN_LS 0x1000000000000000 -#define HID1_EN_CC 0x0800000000000000 -#define HID1_EN_IC 0x0400000000000000 -#define HID1_PF_MASK 0x0180000000000000 -#define HID1_PF_NSA 0x0080000000000000 -#define HID1_PF_NSA_P 0x0100000000000000 -#define HID1_PF_DIS 0x0180000000000000 -#define HID1_EN_ICBI 0x0040000000000000 -#define HID1_EN_IF_CACH 0x0020000000000000 -#define HID1_EN_IC_REC 0x0010000000000000 -#define HID1_EN_ID_REC 0x0008000000000000 -#define HID1_EN_ER_REC 0x0004000000000000 -#define HID1_IC_PE 0x0002000000000000 -#define HID1_ICD0_PE 0x0001000000000000 -#define HID1_ICD1_PE 0x0000800000000000 -#define HID1_IER_PE 0x0000400000000000 -#define HID1_EN_SP_ITW 0x0000200000000000 -#define HID1_S_CHICKEN 0x0000100000000000 - -/*----------------------------------------------------------------------------+ -| HID4 bits. -+----------------------------------------------------------------------------*/ -#define HID4_LPES0 0x8000000000000000 -#define HID4_RMLR12_MSK 0x6000000000000000 -#define HID4_LPID25_MSK 0x1E00000000000000 -#define HID4_RMOR_MASK 0x01FFFE0000000000 -#define HID4_RM_CI 0x0000010000000000 -#define HID4_FORCE_AI 0x0000008000000000 -#define HID4_DIS_PERF 0x0000004000000000 -#define HID4_RES_PERF 0x0000002000000000 -#define HID4_EN_SP_DTW 0x0000001000000000 -#define HID4_L1DC_FLSH 0x0000000800000000 -#define HID4_D_DERAT_P1 0x0000000400000000 -#define HID4_D_DERAT_P2 0x0000000200000000 -#define HID4_D_DERAT_G 0x0000000100000000 -#define HID4_D_DERAT_S1 0x0000000040000000 -#define HID4_D_DERAT_S2 0x0000000080000000 -#define HID4_DC_TP_S1 0x0000000020000000 -#define HID4_DC_TP_S2 0x0000000010000000 -#define HID4_DC_TP_GEN 0x0000000008000000 -#define HID4_DC_SET1 0x0000000004000000 -#define HID4_DC_SET2 0x0000000002000000 -#define HID4_DC_DP_S1 0x0000000001000000 -#define HID4_DC_DP_S2 0x0000000000800000 -#define HID4_DC_DP_GEN 0x0000000000400000 -#define HID4_R_TAG1P_CH 0x0000000000200000 -#define HID4_R_TAG2P_CH 0x0000000000100000 -#define HID4_TLB_PC1 0x0000000000080000 -#define HID4_TLB_PC2 0x0000000000040000 -#define HID4_TLB_PC3 0x0000000000020000 -#define HID4_TLB_PC4 0x0000000000010000 -#define HID4_TLB_P_GEN 0x0000000000008000 -#define HID4_TLB_SET1 0x0000000000003800 -#define HID4_TLB_SET2 0x0000000000005800 -#define HID4_TLB_SET3 0x0000000000006800 -#define HID4_TLB_SET4 0x0000000000007000 -#define HID4_DIS_SLBPC 0x0000000000000400 -#define HID4_DIS_SLBPG 0x0000000000000200 -#define HID4_MCK_INJ 0x0000000000000100 -#define HID4_DIS_STFWD 0x0000000000000080 -#define HID4_LPES1 0x0000000000000040 -#define HID4_RMLR0_MSK 0x0000000000000020 -#define HID4_DIS_SPLARX 0x0000000000000008 -#define HID4_LP_PG_EN 0x0000000000000004 -#define HID4_LPID01_MSK 0x0000000000000003 - -/*----------------------------------------------------------------------------+ -| HID5 bits. -+----------------------------------------------------------------------------*/ -#define HID5_HRMOR_MASK 0x00000000FFFF0000 -#define HID5_DC_MCK 0x0000000000002000 -#define HID5_DIS_PWRSAV 0x0000000000001000 -#define HID5_FORCE_G 0x0000000000000800 -#define HID5_DC_REPL 0x0000000000000400 -#define HID5_HWR_STMS 0x0000000000000200 -#define HID5_DST_NOOP 0x0000000000000100 -#define HID5_DCBZ_SIZE 0x0000000000000080 -#define HID5_DCBZ32_ILL 0x0000000000000040 -#define HID5_TLB_MAP 0x0000000000000020 -#define HID5_IMQ_PORT 0x0000000000000010 -#define HID5_LMP_SIZE0 0x0000000000000008 -#define HID5_DPFLOOD 0x0000000000000004 -#define HID5_TCH_NOP 0x0000000000000002 -#define HID5_LMP_SIZE1 0x0000000000000001 - -/*----------------------------------------------------------------------------+ -| Specific SRR1 bit definitions for Machine Check. -+----------------------------------------------------------------------------*/ -#define SRR1_IFU_UNREC 0x0000000000200000 -#define SRR1_LOAD_STORE 0x0000000000100000 -#define SRR1_SLB_PARITY 0x0000000000040000 -#define SRR1_TLB_PARITY 0x0000000000080000 -#define SRR1_ITLB_RELOA 0x00000000000C0000 -#define SRR1_RI 0x0000000000000002 - -#endif /* _PPC970_H_ */ +/************ ppc970fx_board.h ****************/ + +#ifndef _ppc970_h_ +#define _ppc970_h_ + +/*----------------------------------------------------------------------------+ +| Processor Version Register (PVR) values ++----------------------------------------------------------------------------*/ +#define PVR_970 0x0039 /* 970 any revision*/ +#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */ +#define PVR_970FX 0x003C /* 970FX any revision*/ +#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */ +#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */ +#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */ +#define PVR_RESERVED 0x000000F0 /* reserved nibble */ + +/*----------------------------------------------------------------------------+ +| Supported platforms. ++----------------------------------------------------------------------------*/ +#define PLATFORM_EVB_LITE 3 +#define PLATFORM_EVB_FINAL 4 + +/*----------------------------------------------------------------------------+ +| When timers are running based on CPU speed this is the timer to CPU frequency +| ratio. ++----------------------------------------------------------------------------*/ +#define PPC970_TB_RATIO 8 + +/*----------------------------------------------------------------------------+ +| Cache line size. ++----------------------------------------------------------------------------*/ +#define CACHE_LINE_SIZE_L1 128 +#define CACHE_LINE_SIZE_L2 128 + +/*----------------------------------------------------------------------------+ +| SLB size. ++----------------------------------------------------------------------------*/ +#define SLB_SIZE 64 + +/*----------------------------------------------------------------------------+ +| TLB size. ++----------------------------------------------------------------------------*/ +#define TLB_SIZE 1024 + +/*----------------------------------------------------------------------------+ +| Partial memory map. ++----------------------------------------------------------------------------*/ +#define SDRAM_BASE 0x0000000000000000UL +#define SDRAM_SIZE 0x0000000080000000UL +#define IO_BASE 0x0000000080000000UL +#define IO_SIZE 0x0000000080000000UL +#define PCI_BUS_MEM_BASE 0x0000000080000000UL +#define PCI_BUS_MEM_SIZE 0x0000000070000000UL +#define PCI0_BASE 0x00000000F0000000UL +#define PCI0_SIZE 0x0000000002000000UL +#define HT1_BASE 0x00000000F2000000UL +#define HT1_SIZE 0x0000000003000000UL +#define PPC925_BASE 0x00000000F8000000UL +#define PPC925_SIZE 0x0000000001000000UL +#define SB_IOAPIC_BASE 0x00000000FEC00000UL +#define BOOT_BASE 0x00000000FF000000UL +#define BOOT_BASE_AS 0x00000000FF000000 +#define BOOT_END 0x00000000FFFFFFFFUL +#define FLASH_BASE_INTEL 0x00000000FF800000UL +#define FLASH_BASE_INTEL_AS 0x00000000FF800000 +#define FLASH_BASE_AMD 0x00000000FFF00000UL +#define FLASH_BASE_AMD_AS 0x00000000FFF00000 +#define SDRAM_UPPER_BASE 0x0000000100000000UL +#define SDRAM_UPPER_SIZE 0x0000000F00000000UL + +/*----------------------------------------------------------------------------+ +| BOOT_STACK_ADDR is data used for stack before SDRAM is available. This data +| will be written to memory after the SDRAM is initialized. All values here +| must be less than 32 bits. Following 13 defines need to be changed when +| changing the location of PIBS in SDRAM (the link file also need to be +| changed in order to fully relocate PIBS. ++----------------------------------------------------------------------------*/ +#define PIBS_BASE_ADDR 0x00C00000 +#define BOOT_STACK_ADDR 0x00C50000 +#define BOOT_STACK_SIZE 0x00004000 +#define MEM_CHK_START_ADDR 0x00C40000 +#define MEM_CHK_SIZE 0x00010000 + +/*----------------------------------------------------------------------------+ +| Address of a CPU0, CPU1 shared memory structure. ++----------------------------------------------------------------------------*/ +#define CPU1_DATA_STRUCT_ADDR 0x00C00040 +#define CPU1_DATA_STRUCT_SRR0_OFF 0x00000000 +#define CPU1_DATA_STRUCT_SRR1_OFF 0x00000008 +#define CPU1_DATA_STRUCT_R3_OFF 0x00000010 +#define CPU1_DATA_STRUCT_VALID_OFF 0x00000018 + +/*----------------------------------------------------------------------------+ +| Address of the memory location used for the test and set instruction +| sequence. ++----------------------------------------------------------------------------*/ +#define VM_TEST_AND_SET_ADDR 0x0000000000C000F0UL + +/*----------------------------------------------------------------------------+ +| Initial page table address. ++----------------------------------------------------------------------------*/ +#define INITIAL_PAGE_TABLE_ADDR_CPU0 0x0000000000D00000 +#define INITIAL_PAGE_TABLE_ADDR_CPU1 0x0000000000D40000 +#define INITIAL_PAGE_TABLE_SIZE 0x0000000000040000 + +/*----------------------------------------------------------------------------+ +| Initial stack size. Must be less than 32 bits in length. ++----------------------------------------------------------------------------*/ +#define MY_MAIN_STACK_SIZE (8* 1024) + +/*----------------------------------------------------------------------------+ +| Serial port address. The base address must be programmed into super I/O. The +| external time base is available only on JS20. ++----------------------------------------------------------------------------*/ +#define UART1_MMIO_BASE 0xF40002F8UL +#define UART0_MMIO_BASE 0xF40003F8UL +#define UART1_MMIO_OFFSET 0x2F8; +#define UART0_MMIO_OFFSET 0x3F8; +#define UART_INPUT_CLOCK 1843200 +#define EXT_TIME_BASE_FREQ 0 +#define DIV_HIGH_9600 0x00 +#define DIV_LOW_9600 0x0C + +#define EXT_IRQ_COM1 EXT_SB_HT4 +#define EXT_IRQ_COM2 EXT_SB_HT3 + +/*----------------------------------------------------------------------------+ +| Locations in Super I/O NVRAM where service processor stores information for +| the PPC970FX CPU. ++----------------------------------------------------------------------------*/ +#define SUPER_IO_NVRAM_DATA_VALID 64 +#define SUPER_IO_NVRAM_SYS_CLK (SUPER_IO_NVRAM_DATA_VALID+ 0x04) +#define SUPER_IO_NVRAM_CLK_MULT (SUPER_IO_NVRAM_SYS_CLK+ 0x04) +#define SUPER_IO_NVRAM_EI_RATIO (SUPER_IO_NVRAM_CLK_MULT+ 0x01) + +#define SUPER_IO_VALID_VALUE 0x426F4F6D + +#define PPC970_EI_RATIO_000 2 +#define PPC970_EI_RATIO_001 3 +#define PPC970_EI_RATIO_010 4 +#define PPC970_EI_RATIO_011 6 +#define PPC970_EI_RATIO_100 8 +#define PPC970_EI_RATIO_101 12 +#define PPC970_EI_RATIO_110 16 + +/*----------------------------------------------------------------------------+ +| Locations in Super I/O NVRAM where PPC970 store commands for service +| processor. 0x01 is written by PPC970 to initiate action by the service +| processor. This value is cleared by the service processor upon receiving +| the command. ++----------------------------------------------------------------------------*/ +#define SUPER_IO_NVRAM_POWER_OFF 96 +#define SUPER_IO_NVRAM_RESTART (SUPER_IO_NVRAM_POWER_OFF+ 0x2) + +/*----------------------------------------------------------------------------+ +| Default HID register settings. ++----------------------------------------------------------------------------*/ +#define HID0_PREFEAR 0x0011008180000000 +#define HID1_PREFEAR 0xFD3C200000000000 +#define HID4_PREFEAR 0x0000001000000000 +#define HID5_PREFEAR 0x0000000000000080 + +/*----------------------------------------------------------------------------+ +| Power control SCOM register definitions. ++----------------------------------------------------------------------------*/ +#define SCOM_ADDR_PCR_WRITE 0x000000000AA00000UL +#define SCOM_ADDR_PCR_WRITE_ASM 0x000000000AA00000 +#define SCOM_ADDR_PSR_READ 0x0000000040808000UL +#define SCOM_ADDR_PSR_READ_ASM 0x0000000040808000 + +#define SCOM_ADDR_PCR_DATA_MASK 0x0000000080000000UL +#define SCOM_ADDR_PCR_DATA_MASK_ASM 0x0000000080000000 + +#define SCOM_ADDR_PCR_FREQ_VALID 0x0000000000010000UL +#define SCOM_ADDR_PCR_FREQ_FULL 0x0000000000000000UL +#define SCOM_ADDR_PCR_FREQ_HALF 0x0000000000020000UL +#define SCOM_ADDR_PCR_FREQ_QUARTER 0x0000000000040000UL + +#define SCOM_PSR_FREQ_MASK 0x0300000000000000UL +#define SCOM_PSR_FREQ_FULL 0x0000000000000000UL +#define SCOM_PSR_FREQ_HALF 0x0100000000000000UL +#define SCOM_PSR_FREQ_QUARTER 0x0200000000000000UL +#define SCOM_PSR_COMM_COMPLETED 0x1000000000000000UL +#define SCOM_PSR_COMM_COMPLETED_ASM 0x1000000000000000 + +/*----------------------------------------------------------------------------+ +| Serial port for CPU2 ++----------------------------------------------------------------------------*/ +#define CPU2_SERIAL_PORT 2 +#define CPU2_BAUD_RATE 115200 + +/*----------------------------------------------------------------------------+ +| External interrupt assignments. ++----------------------------------------------------------------------------*/ +#define EXT_I2C_MASTER 0 +#define EXT_VSP 1 +#define EXT_HT1_BRIDGE 2 +#define EXT_PCI0_AGP_BRIDGE 3 +#define EXT_SLEEP0 4 +#define EXT_SLEEP1 5 +#define EXT_SB_HT0 6 +#define EXT_SB_HT1 7 +#define EXT_SB_HT2 8 +#define EXT_SB_HT3 9 +#define EXT_SB_HT4 10 +#define EXT_SB_HT5 11 +#define EXT_SB_HT6 12 +#define EXT_SB_HT7 13 +#define EXT_SB_HT8 14 +#define EXT_SB_HT9 15 +#define EXT_SB_HT10 16 +#define EXT_SB_HT11 17 +#define EXT_SB_HT12 18 +#define EXT_SB_HT13 19 +#define EXT_SB_HT14 20 +#define EXT_SB_HT15 21 +#define EXT_SB_HT16 22 +#define EXT_SB_HT17 23 +#define EXT_SB_HT18 24 +#define EXT_SB_HT19 25 +#define EXT_SB_HT20 26 +#define EXT_SB_HT21 27 +#define EXT_SB_HT22 28 +#define EXT_SB_HT23 29 +#define EXT_SB_HT24 30 +#define EXT_SB_HT25 31 +#define EXT_SB_HT26 32 +#define EXT_SB_HT27 33 +#define EXT_SB_HT28 34 +#define EXT_SB_HT29 35 +#define EXT_SB_HT30 36 +#define EXT_SB_HT31 37 +#define EXT_SB_HT32 38 +#define EXT_SB_HT33 39 +#define EXT_SB_HT34 40 +#define EXT_SB_HT35 41 +#define EXT_SB_HT36 42 +#define EXT_SB_HT37 43 +#define EXT_SB_HT38 44 +#define EXT_SB_HT39 45 +#define EXT_SB_HT40 46 +#define EXT_SB_HT41 47 +#define EXT_SB_HT42 48 +#define EXT_SB_HT43 49 +#define EXT_SB_HT44 50 +#define EXT_SB_HT45 51 +#define EXT_SB_HT46 52 +#define EXT_SB_HT47 53 +#define EXT_SB_HT48 54 +#define EXT_SB_HT49 55 +#define EXT_SB_HT50 56 +#define EXT_SB_HT51 57 +#define EXT_SB_HT52 58 +#define EXT_SB_HT53 59 +#define EXT_SB_HT54 60 +#define EXT_SB_HT55 61 +#define EXT_SB_HT56 62 +#define EXT_SB_HT57 63 +#define EXT_SB_HT58 64 +#define EXT_SB_HT59 65 +#define EXT_SB_HT60 66 +#define EXT_SB_HT61 67 +#define EXT_SB_HT62 68 +#define EXT_SB_HT63 69 +#define EXT_SB_HT64 70 +#define EXT_SB_HT65 71 +#define EXT_SB_HT66 72 +#define EXT_SB_HT67 73 +#define EXT_SB_HT68 74 +#define EXT_SB_HT69 75 +#define EXT_SB_HT70 76 +#define EXT_SB_HT71 77 +#define EXT_SB_HT72 78 +#define EXT_SB_HT73 79 +#define EXT_SB_HT74 80 +#define EXT_SB_HT75 81 +#define EXT_SB_HT76 82 +#define EXT_SB_HT77 83 +#define EXT_SB_HT78 84 +#define EXT_SB_HT79 85 +#define EXT_SB_HT80 86 +#define EXT_SB_HT81 87 +#define EXT_SB_HT82 88 +#define EXT_SB_HT83 89 +#define EXT_SB_HT84 90 +#define EXT_SB_HT85 91 +#define EXT_SB_HT86 92 +#define EXT_SB_HT87 93 +#define EXT_SB_HT88 94 +#define EXT_SB_HT90 95 +#define EXT_SB_HT91 96 +#define EXT_SB_HT92 97 +#define EXT_SB_HT93 98 +#define EXT_SB_HT94 99 +#define EXT_SB_HT95 100 +#define EXT_SB_HT96 101 +#define EXT_SB_HT97 102 +#define EXT_SB_HT98 103 +#define EXT_SB_HT99 104 +#define EXT_SB_HT100 105 +#define EXT_SB_HT101 106 +#define EXT_SB_HT102 107 +#define EXT_SB_HT103 108 +#define EXT_SB_HT104 109 +#define EXT_SB_HT105 110 +#define EXT_SB_HT106 111 +#define EXT_SB_HT107 112 +#define EXT_SB_HT108 113 +#define EXT_SB_HT109 114 +#define EXT_SB_HT110 115 +#define EXT_SB_HT111 116 +#define EXT_SB_HT112 117 +#define EXT_SB_HT113 118 +#define EXT_SB_HT114 119 +#define EXT_SB_HT115 120 +#define EXT_SB_HT116 121 +#define EXT_SB_HT117 122 +#define EXT_SB_HT118 123 +#define EXT_IPI_0 124 +#define EXT_IPI_1 125 +#define EXT_MAX_IRQ_NUM 125 + +/*----------------------------------------------------------------------------+ +| # # # ###### ####### +| # # # # # # # +| # # # # # # # +| # # # # ###### # +| # # ####### # # # +| # # # # # # # +| ##### # # # # # ++----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------+ +| Interrupt Enable Register. DLAB must be set to 0 access this register. ++----------------------------------------------------------------------------*/ +#define asyncIER 1 +#define asyncIERModem 0x08 +#define asyncIERLine 0x04 +#define asyncIERTransmit 0x02 +#define asyncIERReceive 0x01 +#define asyncIERdisableAll 0x00 + +/*----------------------------------------------------------------------------+ +| Interrupt Identification Register. Read only register. ++----------------------------------------------------------------------------*/ +#define asyncIIR 2 +#define asyncIIRMask 0x0F +#define asyncIIRFifoTimeout 0x0C +#define asyncIIRLine 0x06 +#define asyncIIRReceive 0x04 +#define asyncIIRTransmit 0x02 +#define asyncIIRNoInterrupt 0x01 +#define asyncIIRModem 0x00 + +/*----------------------------------------------------------------------------+ +| FIFO Control Register. Write only register. ++----------------------------------------------------------------------------*/ +#define asyncFCR 2 +#define asyncFCRFifoTrigger14 0xC0 +#define asyncFCRFifoTrigger8 0x80 +#define asyncFCRFifoTrigger4 0x40 +#define asyncFCRFifoTrigger1 0x00 +#define asyncFCRDmaSet 0x08 +#define asyncFCRClearXmitFifo 0x04 +#define asyncFCRClearRcvFifo 0x02 +#define asyncFCRFifoEnable 0x01 + +/*----------------------------------------------------------------------------+ +| Line Control Register. ++----------------------------------------------------------------------------*/ +#define asyncLCR 3 +#define asyncLCRDLAB 0x80 +#define asyncLCRSetBreak 0x40 +#define asyncLCRStickParity 0x20 +#define asyncLCREvenParity 0x10 +#define asyncLCROddParity 0x00 +#define asyncLCRParityEnable 0x08 +#define asyncLCRParityDisable 0x00 +#define asyncLCRStopBitsTwo 0x04 +#define asyncLCRStopBitsOne 0x00 +#define asyncLCRWordLengthSel 0x03 +#define asyncLCRWordLength5 0x00 +#define asyncLCRWordLength6 0x01 +#define asyncLCRWordLength7 0x02 +#define asyncLCRWordLength8 0x03 + +/*----------------------------------------------------------------------------+ +| Modem Control Register. ++----------------------------------------------------------------------------*/ +#define asyncMCR 4 +#define asyncMCRLoop 0x10 +#define asyncMCROut2 0x08 +#define asyncMCROut1 0x04 +#define asyncMCRRTS 0x02 +#define asyncMCRDTR 0x01 +#define asyncMCRdisableAll 0x00 + +/*----------------------------------------------------------------------------+ +| Line Status Register. ++----------------------------------------------------------------------------*/ +#define asyncLSR 5 +#define asyncLSRRxFifoError 0x80 +#define asyncLSRTxEmpty 0x60 +#define asyncLSRTxShiftEmpty 0x40 +#define asyncLSRTxHoldEmpty 0x20 +#define asyncLSRBreakInterrupt 0x10 +#define asyncLSRFramingError 0x08 +#define asyncLSRParityError 0x04 +#define asyncLSROverrunError 0x02 +#define asyncLSRDataReady 0x01 + +/*----------------------------------------------------------------------------+ +| Modem Status Register. Read only register. ++----------------------------------------------------------------------------*/ +#define asyncMSR 6 +#define asyncMSRCD 0x80 +#define asyncMSRRI 0x40 +#define asyncMSRDSR 0x20 +#define asyncMSRCTS 0x10 +#define asyncMSRDeltaDCD 0x08 +#define asyncMSRDeltaRI 0x04 +#define asyncMSRDeltaDSR 0x02 +#define asyncMSRDeltaCTS 0x01 + +/*----------------------------------------------------------------------------+ +| Miscellanies defines. ++----------------------------------------------------------------------------*/ +#define asyncScratchReg 7 +#define asyncTxBuffer 0 +#define asyncRxBuffer 0 +#define asyncDLABLsb 0 +#define asyncDLABMsb 1 + +/*----------------------------------------------------------------------------+ +| ##### ###### ##### ##### ##### ####### +| # # # # # # # # # # # +| # # # # # # # # +| # ###### # ###### ##### ###### +| # # # # # # +| # # # # # # # # # # +| ##### # ##### ##### ####### ##### ++----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------+ +| When performing PCI configuration read/write the configuration address +| register must be written and then read before configuration data register is +| accessed. +| PCI type 0 Configuration address format is: +| 0-20 id. sel., 21-23 function number, 24-29 register number|00 ++----------------------------------------------------------------------------*/ +#define NB_PCI_CONFIGURATION_ADDR 0x0F0800000UL +#define NB_PCI_CONFIGURATION_DATA 0x0F0C00000UL + +/*----------------------------------------------------------------------------+ +| When performing HT configuration read/write the configuration address +| register must be written and then read before configuration data register is +| accessed. +| HT type 0 Configuration address format is: +| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|00 +| HT type 1 configuration address format is +| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|01 ++----------------------------------------------------------------------------*/ +#define NB_HT_CONFIGURATION_ADDR 0x0F2800000UL +#define NB_HT_CONFIGURATION_DATA 0x0F2C00000UL + +/*----------------------------------------------------------------------------+ +| HT Configuration Address Spaces. ++----------------------------------------------------------------------------*/ +#define NB_HT_CONFIG_TYPE_0_BASE 0x0F2000000UL +#define NB_HT_CONFIG_TYPE_1_BASE 0x0F3000000UL + +/*----------------------------------------------------------------------------+ +| HT I/O Space. NB_HT_IO_RESERVED is reserved for Super I/O peripherals. The +| SuperI/O utilizes subtractive decode. All PCI I/0 addresses are translated +| from 0xF4xxxxxx (CPU) to 0x00xxxxxx (PCI). ++----------------------------------------------------------------------------*/ +#define NB_HT_IO_BASE_CPU 0x0F4000000UL +#define NB_HT_IO_BASE_BYTE 0xF4 +#define NB_HT_IO_BASE_BYTE_SH 24 +#define NB_HT_IO_BASE_PCI 0x000000000UL +#define NB_HT_IO_BASE_ASM 0xF4000000 +#define NB_HT_IO_SIZE 0x000400000UL +#define NB_HT_IO_RESERVED 0x000010000UL + +/*----------------------------------------------------------------------------+ +| HT EOI Space. ++----------------------------------------------------------------------------*/ +#define NB_HT_EOI_BASE 0x0F4400000UL +#define NB_HT_EOI_SIZE 0x000400000UL + +/*----------------------------------------------------------------------------+ +| HT Device Header Regs. Big Endian. ++----------------------------------------------------------------------------*/ +#define NB_HT_REG_BASE 0x0F8070000UL +#define NB_HT_DID_VID 0x0F8070000UL +#define NB_HT_STAT_CMD 0x0F8070010UL +#define NB_HT_CLASS_REV 0x0F8070020UL +#define NB_HT_BIST_HT 0x0F8070030UL +#define NB_HT_CAP_PTR 0x0F80700D0UL +#define NB_HT_INT_LINE 0x0F80700F0UL + +/*----------------------------------------------------------------------------+ +| HT Capabilities Block. Big Endian. ++----------------------------------------------------------------------------*/ +#define NB_HT_CMD_PTR_ID 0x0F8070100UL +#define HT_WARM_RESET 0x00010000 +#define NB_HT_LINK_CFG_CONTROL 0x0F8070110UL +#define HT_CRC_ERR 0x00000F00 +#define HT_END_OF_CHAIN 0x00000040 +#define HT_INIT 0x00000020 +#define HT_LINK_FAIL 0x00000010 +#define HT_LINK_OUT_MASK 0x70000000 +#define HT_LINK_IN_MASK 0x07000000 +#define HT_LINK_MAX_OUT_MASK 0x00700000 +#define HT_LINK_MAX_IN_MASK 0x00070000 +#define HT_LINK_WIDTH_8_BIT 0x0 +#define HT_LINK_WIDTH_16_BIT 0x1 +#define HT_LINK_WIDTH_32_BIT 0x3 +#define HT_LINK_WIDTH_2_BIT 0x4 +#define HT_LINK_WIDTH_4_BIT 0x5 +#define NB_HT_LINK_FREQ_ERROR 0x0F8070120UL +#define HT_LINK_FREQ_CAP_MASK 0xFFFF0000 +#define HT_LINK_FREQ_MASK 0x00000F00 +#define HT_LINK_FREQ_200 0x0 +#define HT_LINK_FREQ_300 0x1 +#define HT_LINK_FREQ_400 0x2 +#define HT_LINK_FREQ_500 0x3 +#define HT_LINK_FREQ_600 0x4 +#define HT_LINK_FREQ_800 0x5 +#define HT_LINK_FREQ_1000 0x6 + +/*----------------------------------------------------------------------------+ +| HT Other registers. Big Endian. ++----------------------------------------------------------------------------*/ +#define NB_HT_ADDRESS_MASK 0x0F8070200UL +#define NB_HT_PROCESSOR_INT_CONTROL 0x0F8070210UL +#define NB_HT_BRIDGE_CONTROL 0x0F8070300UL +#define HT_SECBUSRESET 0x00400000 +#define NB_HT_TXCTL_DATABUFALLOC 0x0F8070310UL +#define NB_HT_TXBUFCOUNTMAX 0x0F8070340UL + +/*----------------------------------------------------------------------------+ +| Accessed through AGP/PCI configuration space on PCI0 bus. ++----------------------------------------------------------------------------*/ +#define NB_PCI_ADDRESS_MASK 0x48 +#define NB_PCI_ADDRESS_MASK_RVALUE 0x00000003 + +/*----------------------------------------------------------------------------+ +| MPIC ++----------------------------------------------------------------------------*/ +#define NB_MPIC_TOGGLE 0x0F80000E0UL +#define NB_MPIC_ENABLE_OUT 0x00000004 +#define NB_MPIC_RESET 0x00000002 + +#define NB_MPIC_BASE 0x0F8040000UL +#define NB_MPIC_SIZE 0x000040000UL + +#define NB_MPIC_FEATURE 0x0F8041000UL +#define NB_MPIC_GLOBAL0 0x0F8041020UL +#define NB_MPIC_GLOBAL0_MPIC_RESET 0x80000000U +#define NB_MPIC_IPI0_VECT_PRIO 0x0F80410A0UL +#define NB_MPIC_IPI1_VECT_PRIO 0x0F80410B0UL +#define NB_MPIC_SPURIOUS_VECTOR 0x0F80410E0UL + +#define NB_MPIC_S0_VECT_PRIO 0x0F8050000UL +#define NB_MPIC_VECT_PRIO_ADDER 0x00000020 +#define NB_MPIC_S0_DESINATION 0x0F8050010UL +#define NB_MPIC_DESINATION_ADDER 0x00000020 + +#define NB_MPIC_P0_IPI0_DISPATCH 0x0F8060040UL +#define NB_MPIC_P0_IPI1_DISPATCH 0x0F8060050UL +#define NB_MPIC_P0_TASK_PRIO 0x0F8060080UL +#define NB_MPIC_P0_INT_ACK 0x0F80600A0UL +#define NB_MPIC_P0_INT_ACK_AS 0x0F80600A0 +#define NB_MPIC_P0_EIO 0x0F80600B0UL +#define NB_MPIC_P0_EIO_AS 0x0F80600B0 +#define NB_MPIC_P1_IPI0_DISPATCH 0x0F8061040UL +#define NB_MPIC_P1_IPI1_DISPATCH 0x0F8061050UL +#define NB_MPIC_P1_TASK_PRIO 0x0F8061080UL +#define NB_MPIC_P1_INT_ACK 0x0F80610A0UL +#define NB_MPIC_P1_INT_ACK_AS 0x0F80610A0 +#define NB_MPIC_P1_EIO 0x0F80610B0UL +#define NB_MPIC_P1_EIO_AS 0x0F80610B0 + +#define NB_MPIC_IPI_PRIO_MASK 0x000F0000 +#define NB_MPIC_IPI_PRIO_SH 16 +#define NB_MPIC_IPI_VECTOR_MASK 0x000000FF +#define NB_MPIC_IPI_MASK 0x80000000U +#define NB_MPIC_IPI_ACTIVE 0x40000000 + +#define NB_MPIC_EXT_PRIO_MASK 0x000F0000 +#define NB_MPIC_EXT_PRIO_SH 16 +#define NB_MPIC_EXT_VECTOR_MASK 0x000000FF +#define NB_MPIC_EXT_MASK 0x80000000U +#define NB_MPIC_EXT_ACTIVE 0x40000000 +#define NB_MPIC_EXT_SENSE 0x00400000 + +#define NB_MPIC_DEST_CPU0 0x00000001 +#define NB_MPIC_DEST_CPU1 0x00000002 + +#define NB_MPIC_IPI_CPU0 0x00000001 +#define NB_MPIC_IPI_CPU1 0x00000002 + +#define NB_MPIC_TASK_PRIO_MASK 0x0000000F + +#define NB_MPIC_C0_CASCADE 0x20000000 + +/*----------------------------------------------------------------------------+ +| I2C ++----------------------------------------------------------------------------*/ +#define NB_IIC_MMIO_BASE 0xF8001000UL +#define NB_IIC_MMIO_BASE_BYTE4 0xF8 +#define NB_IIC_MMIO_BASE_BYTE5 0x00 +#define NB_IIC_MMIO_BASE_BYTE6 0x10 +#define NB_IIC_MMIO_BASE_BYTE7 0x00 +#define NB_IIC_MMIO_BASE_MASK 0xFFFFFFFF +#define NB_IIC_MMIO_SIZE 0x00001000UL +#define NB_IIC_MODE 0x00 +#define NB_IIC_CNTRL 0x10 +#define NB_IIC_STATUS 0x20 +#define NB_IIC_ISR 0x30 +#define NB_IIC_IER 0x40 +#define NB_IIC_ADDR 0x50 +#define NB_IIC_SUBADDR 0x60 +#define NB_IIC_DATA 0x70 +#define NB_IIC_REV 0x80 +#define NB_IIC_RISETTIMECNT 0x90 +#define NB_IIC_BITTIMECNT 0xA0 + +#define IIC_MODE_PORTSEL0 0x00000000 +#define IIC_MODE_PORTSEL1 0x00000010 +#define IIC_MODE_APMODE_MANUAL 0x00000000 +#define IIC_MODE_APMODE_STANDARD 0x00000004 +#define IIC_MODE_APMODE_SUBADDR 0x00000008 +#define IIC_MODE_APMODE_COMBINED 0x0000000C +#define IIC_MODE_SPEED_25 0x00000002 +#define IIC_MODE_SPEED_50 0x00000001 +#define IIC_MODE_SPEED_100 0x00000000 + +#define IIC_CNTRL_STOP 0x00000004 +#define IIC_CNTRL_XADDR 0x00000002 +#define IIC_CNTRL_AAK 0x00000001 + +#define IIC_STATUS_LASTAAK 0x00000002 + +#define IIC_ISR_ISTOP 0x00000004 +#define IIC_ISR_IADDR 0x00000002 +#define IIC_ISR_IDATA 0x00000001 + +/*----------------------------------------------------------------------------+ +| DDR_SDRAM Controller ++----------------------------------------------------------------------------*/ +#define NB_SDRAM_BASE 0xF8002000UL +#define NB_SDRAM_BASE_BYTE4 0xF8 +#define NB_SDRAM_BASE_BYTE5 0x00 +#define NB_SDRAM_BASE_BYTE6 0x20 +#define NB_SDRAM_BASE_BYTE7 0x00 +#define NB_SDRAM_BASE_MASK 0xFFFFFFFF +#define NB_SDRAM_SIZE 0x00001000UL +#define NB_SDRAM_MEMTIMINGPARAM 0x050 +#define NB_SDRAM_MEMPROGCNTL 0x0E0 +#define NB_SDRAM_MRS 0x0F0 +#define NB_SDRAM_MRSREGCNTL 0x0F0 +#define NB_SDRAM_EMRS 0x100 +#define NB_SDRAM_EMRSREGCNTL 0x100 +#define NB_SDRAM_MEMBUSCFG 0x190 +#define NB_SDRAM_MEMMODE0 0x1C0 +#define NB_SDRAM_MEMBOUNDAD0 0x1D0 +#define NB_SDRAM_MEMMODE1 0x1E0 +#define NB_SDRAM_MEMBOUNDAD1 0x1F0 +#define NB_SDRAM_MEMMODE2 0x200 +#define NB_SDRAM_MEMBOUNDAD2 0x210 +#define NB_SDRAM_MEMMODE3 0x220 +#define NB_SDRAM_MEMBOUNDAD3 0x230 +#define NB_SDRAM_MEMMODE4 0x240 +#define NB_SDRAM_MEMBOUNDAD4 0x250 +#define NB_SDRAM_MEMMODE5 0x260 +#define NB_SDRAM_MEMBOUNDAD5 0x270 +#define NB_SDRAM_MEMMODE6 0x280 +#define NB_SDRAM_MEMBOUNDAD6 0x290 +#define NB_SDRAM_MEMMODE7 0x2A0 +#define NB_SDRAM_MEMBOUNDAD7 0x2B0 +#define NB_SDRAM_MSCR 0x400 +#define NB_SDRAM_MSRSR 0x410 +#define NB_SDRAM_MSRER 0x420 +#define NB_SDRAM_MSPR 0x430 +#define NB_SDRAM_MCCR 0x440 +#define NB_SDRAM_MEMMODECNTL 0x500 +#define NB_SDRAM_DELMEASSTATE 0x510 +#define NB_SDRAM_CKDELADJ 0x520 +#define NB_SDRAM_IOMODECNTL 0x530 +#define NB_SDRAM_DQSDELADJ0 0x600 +#define NB_SDRAM_DQSDATADELADJ0 0x610 + +#define SDRAM_MEMORY_MODE_256M_16Mx16 0x0A000000 +#define SDRAM_MEMORY_MODE_256M_32Mx8 0x0C000000 +#define SDRAM_MEMORY_MODE_512M_64Mx8 0x0E000000 +#define SDRAM_MEMORY_MODE_1G_64Mx16 0x10000000 +#define SDRAM_MEMORY_MODE_1G_128Mx8 0x12000000 + +#define SDRAM_MEMMODE_BANKEN 0x40000000 +#define SDRAM_MEMMODE_BASEBANKADDR 0x01000000 +#define SDRAM_MEMMODE_LSSIDE 0x00800000 +#define SDRAM_MEMMODE_HSSIDE 0x00400000 + +#define SDRAM_MEMBOUNDAD_BASEBANKADDR 0xFF000000 + +#define SDRAM_MEMPROGCNTL_SL 0x80000000 +#define SDRAM_MEMPROGCNTL_WDR 0x40000000 + +#define SDRAM_MTP_RCD_MASK 0xE0000000 +#define SDRAM_MTP_RP_MASK 0x1C000000 +#define SDRAM_MTP_RAS_MASK 0x03800000 +#define SDRAM_MTP_WRT 0x00400000 +#define SDRAM_MTP_RFC_MASK 0x003C0000 +#define SDRAM_MTP_WRCD 0x00020000 +#define SDRAM_MTP_CAS_RR_MASK 0x0001C000 +#define SDRAM_MTP_CAS_RW_MASK 0x00003800 +#define SDRAM_MTP_TRFCX2 0x00000400 + +#define SDRAM_MTP_RCD_2 0x20000000 +#define SDRAM_MTP_RCD_3 0x40000000 +#define SDRAM_MTP_RCD_4 0x60000000 +#define SDRAM_MTP_RCD_5 0x80000000 +#define SDRAM_MTP_RCD_6 0xA0000000 +#define SDRAM_MTP_RP_2 0x04000000 +#define SDRAM_MTP_RP_3 0x08000000 +#define SDRAM_MTP_RP_4 0x0C000000 +#define SDRAM_MTP_RP_5 0x10000000 +#define SDRAM_MTP_RP_6 0x14000000 +#define SDRAM_MTP_RAS_4 0x00000000 +#define SDRAM_MTP_RAS_5 0x00800000 +#define SDRAM_MTP_RAS_6 0x01000000 +#define SDRAM_MTP_RAS_7 0x01800000 +#define SDRAM_MTP_RAS_8 0x02000000 +#define SDRAM_MTP_CAS_RR_2 0x00008000 +#define SDRAM_MTP_CAS_RR_3 0x0000C000 +#define SDRAM_MTP_CAS_RR_4 0x00010000 +#define SDRAM_MTP_CAS_RR_5 0x00014000 +#define SDRAM_MTP_CAS_RR_25 0x00018000 +#define SDRAM_MTP_CAS_RW_2 0x00001000 +#define SDRAM_MTP_CAS_RW_3 0x00001800 +#define SDRAM_MTP_CAS_RW_4 0x00002000 +#define SDRAM_MTP_CAS_RW_5 0x00002800 +#define SDRAM_MTP_CAS_RW_25 0x00003000 + +#define SDRAM_MRS_LTMODE_MASK 0x00000070 +#define SDRAM_MRS_LTMODE_20 0x00000020 +#define SDRAM_MRS_LTMODE_25 0x00000060 +#define SDRAM_MRS_BT 0x00000008 +#define SDRAM_MRS_BL4 0x00000002 + +#define SDRAM_MMCR_REGISTERED_MASK 0x14400000 + +#define SDRAM_MSCR_SCRUBMODOFF 0x00000000 +#define SDRAM_MSCR_SCRUBMODBACKG 0x40000000 +#define SDRAM_MSCR_SCRUBMODIMMED 0x80000000 +#define SDRAM_MSCR_SCRUBMODIMMEDFILL 0xC0000000 +#define SDRAM_MSCR_SI_MASK 0x00FF0000 + +#define SDRAM_MCCR_ECC_EN 0x80000000 +#define SDRAM_MCCR_ECC_APP_DIS 0x40000000 +#define SDRAM_MCCR_EI_EN_H 0x20000000 +#define SDRAM_MCCR_EI_EN_L 0x10000000 +#define SDRAM_MCCR_ECC_UE_MASK_H 0x08000000 +#define SDRAM_MCCR_ECC_CE_MASK_H 0x04000000 +#define SDRAM_MCCR_ECC_UE_MASK_L 0x02000000 +#define SDRAM_MCCR_ECC_CE_MASK_L 0x01000000 +#define SDRAM_MCCR_EI_PAT_H 0x0000FF00 +#define SDRAM_MCCR_EI_PAT_L 0x000000FF + +/*----------------------------------------------------------------------------+ +| Power Management ++----------------------------------------------------------------------------*/ +#define NB_CLOCK_CTL 0xF8000F00UL +#define HT_LOGIC_STOP_EN 0x00000010 +#define HT_CLK_EN 0x00000008 +#define NB_PLL2 0xF8000F60UL +#define NB_PLL2_BYTE4 0xF8 +#define NB_PLL2_BYTE5 0x00 +#define NB_PLL2_BYTE6 0x0F +#define NB_PLL2_BYTE7 0x60 +#define NB_PLL2_MASK 0xFFFFFFFF +#define PLL2_FORCEPLLLOAD 0x40000000 +#define PLL2_VALUES_MASK 0x0F01F3FF +#define PLL2_266 0x021082B8 +#define PLL2_300 0x021092B8 +#define PLL2_333 0x0210A2B8 +#define PLL2_FEEDBACK_MASK 0x0001F000 +#define PLL2_FEEDBACK_SPEED_266 0x00008000 +#define PLL2_FEEDBACK_SPEED_300 0x00009000 +#define PLL2_FEEDBACK_SPEED_333 0x0000A000 +#define PLL2_FEEDBACK_SPEED_366 0x0000B000 +#define PLL2_FEEDBACK_SPEED_400 0x0000C000 +#define PLL2_FEEDBACK_SPEED_433 0x0000D000 +#define PLL2_FEEDBACK_SPEED_466 0x0000E000 +#define PLL2_FEEDBACK_SPEED_500 0x0000F000 +#define NB_PLL4 0xF8000F80UL +#define PLL4_FORCEPLLLOAD 0x40000000 + +/*----------------------------------------------------------------------------+ +| CPC925 Control ++----------------------------------------------------------------------------*/ +#define NB_REVISION 0xF8000000UL +#define CPC925_DD1_1 0x00000035 +#define NB_WHOAMI 0xF8000050UL +#define NB_SEMAPHORE 0xF8000060UL +#define NB_HW_INIT_STATE 0xF8000070UL +#define NB_HW_INIT_STATE_ASM 0xF8000070 + +/*----------------------------------------------------------------------------+ +| DART ++----------------------------------------------------------------------------*/ +#define NB_DART_BASE 0xF8033000UL +#define NB_DART_SIZE 0x00007000UL + +/*----------------------------------------------------------------------------+ +| ##### # # ###### ####### ###### ### ####### +| # # # # # # # # # # # # +| # # # # # # # # # # # +| ##### # # ###### ##### ###### # # # +| # # # # # # # # # # +| # # # # # # # # # # # +| ##### ##### # ####### # # ####### ### ####### ++----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------+ +| Configuration registers. ++----------------------------------------------------------------------------*/ +#define SUPER_IO_INDEX_OFF 0x2E +#define SUPER_IO_DATA_OFF 0x2F + +#define SUPER_SST_IO_INDEX_OFF 0x2E +#define SUPER_SST_IO_DATA_OFF 0x2F + +#define SUPER_IO_DEVICE_SEL 0x07 + +#define SUPER_IO_DEVICE_S1 3 +#define SUPER_IO_DEVICE_S2 2 +#define SUPER_IO_DEVICE_XBUS 15 +#define SUPER_IO_DEVICE_RTC 16 + +#define SUPER_IO_ADDR_XBUS 0x800 +#define SUPER_IO_ADDR_RTC 0x900 +#define SUPER_IO_ADDR_NVRAM 0x902 + +#define SUPER_IO_DEVICE_CTRL 0x30 +#define SUPER_IO_BASE_DEV_MSB 0x60 +#define SUPER_IO_BASE_DEV_LSB 0x61 +#define SUPER_IO_EXT_DEV_MSB 0x62 +#define SUPER_IO_EXT_DEV_LSB 0x63 +#define SUPER_IO_INT_NUM 0x70 +#define SUPER_IO_INT_TYPE 0x71 + +#define SUPER_IO_SERIAL_CONFIG 0xF0 + +#define SUPER_IO_XBUS_CONFIG 0xF8 +#define SUPER_IO_BIOS_SIZE_16M 0x06 +#define SUPER_IO_BIOS_SIZE_1M 0x02 + +#define SUPER_IO_XBUS_HOST_ACCESS (SUPER_IO_ADDR_XBUS+ 0x13) + +#define SUPER_IO_RTC_DATE_ALARM_OFF 0xF1 +#define SUPER_IO_RTC_MONTH_ALARM_OFF 0xF2 +#define SUPER_IO_RTC_CENTURY_ALARM_OFF 0xF3 + +#define SUPER_IO_RTC_DATE_ALARM_LOC 0x0D +#define SUPER_IO_RTC_MONTH_ALARM_LOC 0x0E +#define SUPER_IO_RTC_CENTURY_ALARM_LOC 0x0F + +#define SUPER_IO_DEVICE_ENABLE 0x01 + +#define SUPER_IO_SST_START_CONFIG 0x55 +#define SUPER_IO_SST_STOP_CONFIG 0xAA + +#define SUPER_IO_SST_ID_INDEX 0x20 +#define SUPER_IO_SST_ID_VALUE 0x51 + +#define SUPER_IO_SST_DEVICE_INDEX 0x07 +#define SUPER_IO_SST_DEVICE_S1 0x04 +#define SUPER_IO_SST_DEVICE_S2 0x05 +#define SUPER_IO_SST_DEVICE_RUNTIME 0x0A + +#define SUPER_IO_INT_SELECT 0x70 +#define SUPER_IO_INT_SERIAL_1 0x04 +#define SUPER_IO_INT_SERIAL_2 0x03 + +#define SUPER_IO_SST_RUNTIME_REGS 0x100 + +#define SUPER_IO_BASE_CLOCKL32 0xF0 + +#define SUPER_IO_BASE_CLOCKL32_ALL_OFF 0x03 + +#define SUPER_IO_SST_GPIO_52 0x41 +#define SUPER_IO_SST_GPIO_53 0x42 + +#define SUPER_IO_SST_GPIO_60 0x47 +#define SUPER_IO_SST_GPIO_61 0x48 + +#define SUPER_IO_SST_GPIO_LED1 0x5D +#define SUPER_IO_SST_GPIO_LED2 0x5E + +#define SEPER_IO_SST_RX 0x05 +#define SEPER_IO_SST_TX 0x04 + +#define SEPER_IO_SST_LED1 0x06 +#define SEPER_IO_SST_LED2 0x06 + +#define SEPER_IO_SST_LED_ONE_HZ 0x01 +#define SEPER_IO_SST_LED_HALF_HZ 0x02 + +/*----------------------------------------------------------------------------+ +| # # # ###### ##### # ##### # +| # # ## ## # # # # ## # # ## +| # # # # # # # # # # # # # # # +| # # # # # # # ##### # ##### # +| ####### # # # # # # # # # +| # # # # # # # # # # # # +| # # # # ###### ##### ##### ##### ##### ++----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------+ +| PCI register information. ++----------------------------------------------------------------------------*/ +#define HTT_BRIDGE_ID ((unsigned int)0x7450) +#define HTT_IOAPIC_ID ((unsigned int)0x7451) + +#define HTT_INDEX_OFF 0xB8 +#define HTT_DATA_OFF 0xBC +#define HTT_IOAPIC_CTRL 0x44 +#define HTT_PREF_CONFIG_REG 0x4C +#define HTT_LINK_CFG_A 0xC4 +#define HTT_LINK_CFG_B 0xC8 +#define HTT_LINK_FREQ_CAP_A 0xCC +#define HTT_SEC_STATUS_REG 0xA0 +#define HTT_LINK_FREQ_CAP_B 0xD0 + +/*----------------------------------------------------------------------------+ +| # # # ###### ##### # # # +| # # ## ## # # # # ## ## ## +| # # # # # # # # # # # # # # # # +| # # # # # # # ##### # # # +| ####### # # # # # # # # # +| # # # # # # # # # # # +| # # # # ###### ##### ##### ##### ##### ++----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------+ +| PCI register information. ++----------------------------------------------------------------------------*/ +#define AMD_VENDOR_ID ((unsigned int)0x1022) +#define SB_LPCB_DEV_ID ((unsigned int)0x7468) +#define SB_SYSM_DEV_ID ((unsigned int)0x746B) +#define SB_PCIB_DEV_ID ((unsigned int)0x7460) +#define SB_USB_DEV_ID ((unsigned int)0x7464) +#define SB_EHC_DEV_ID ((unsigned int)0x7463) +#define SB_ENET_DEV_ID ((unsigned int)0x7462) +#define SB_IDE_DEV_ID ((unsigned int)0x7469) +#define SB_SMB_DEV_ID ((unsigned int)0x746A) +#define SB_AC97AUDIO_DEV_ID ((unsigned int)0x746D) +#define SB_AC97MODEM_DEV_ID ((unsigned int)0x746E) + +#define SB_R_IO_CTRL1 0x40 +#define SB_R_LEG_CTRL 0x42 +#define SB_R_ROM_DECODE 0x43 +#define SB_R_MISC_CTRL 0x47 +#define SB_R_FUNC_ENABLE 0x48 +#define SB_R_IOAPIC_C0 0x4A +#define SB_R_IOAPIC_C1 0x4B +#define SB_R_SCICONFIG 0x42 +#define SB_R_PNP_IRQ_SEL 0x44 +#define SB_R_SERIRQ_CONNF 0x4A +#define SB_R_PCI_PREF_C0 0x50 +#define SB_R_PCI_PREF_C1 0x54 +#define SB_R_PCI_IRQ_ROUTE 0x56 +#define SB_R_NVCTRL 0x74 + +#define SB_LPC_ROM_W 0x01 +#define SB_LPC_ROM_SIZE 0xC0 +#define SB_PCI_PR_C0 0x00000000 +#define SB_PCI_PR_C1 0x0000718D +#define SB_NVRAM_EN 0xDE01 + +#define SB_SYSM_CC_WRITE 0x60 + +#define SB_NVRAM_ADDR (NB_HT_IO_BASE_CPU+ 0xDE00) + +/*----------------------------------------------------------------------------+ +| IDE controller ++----------------------------------------------------------------------------*/ +#define SB_IDE_PRI_BASE (NB_HT_IO_BASE_CPU+ 0x1F0) +#define SB_IDE_SEC_BASE (NB_HT_IO_BASE_CPU+ 0x170) +#define SB_IDE_DATA (NB_HT_IO_BASE_CPU+ 0x1F0) +#define SB_IDE_CNT (NB_HT_IO_BASE_CPU+ 0x1F2) +#define SB_IDE_LBAL (NB_HT_IO_BASE_CPU+ 0x1F3) +#define SB_IDE_LBAM (NB_HT_IO_BASE_CPU+ 0x1F4) +#define SB_IDE_LBAH (NB_HT_IO_BASE_CPU+ 0x1F5) +#define SB_IDE_DEV (NB_HT_IO_BASE_CPU+ 0x1F6) + +/*----------------------------------------------------------------------------+ +| Write. ++----------------------------------------------------------------------------*/ +#define SB_IDE_CMD (NB_HT_IO_BASE_CPU+ 0x1F7) + +/*----------------------------------------------------------------------------+ +| Read. ++----------------------------------------------------------------------------*/ +#define SB_IDE_STAT (NB_HT_IO_BASE_CPU+ 0x1F7) +#define SB_IDE_CTRL (NB_HT_IO_BASE_CPU+ 0x3F6) + +#define IDE_STAT_BSY 0x80 +#define IDE_DEV_LBA 0x40 +#define IDE_DEV_HEAD_MASK 0x0F +#define IDE_CMD_READ_RETRIES 0x20 +#define IDE_CTRL_NIEN 0x02 + +#define IDE_RANGE_LEGACY 0xCC00 + +#define SB_EIDEC_CMD 0x04 +#define SB_EIDEC_PROG 0x08 +#define SB_EIDEC_INT 0x3C +#define SB_EIDEC_CONFIG 0x40 + +#define EIDEC_CMD_BMEN 0x00000004 +#define EIDEC_CMD_IOEN 0x00000001 +#define EIDEC_PROG_PROGIF2 0x00000400 +#define EIDEC_PROG_PROGIF0 0x00000100 +#define EIDEC_CONFIG_PRIEN 0x00000002 +#define EIDEC_CONFIG_SECEN 0x00000001 + +/*----------------------------------------------------------------------------+ +| LPC bus. ++----------------------------------------------------------------------------*/ +#define SB_LPC_FUNCENAB 0x48 +#define LPC_FUNCENAB_IDE 0x0002 + +#define SB_RTC_LEG_ADDR 0x70 +#define SB_RTC_LEG_DATA 0x71 + +/*----------------------------------------------------------------------------+ +| RTC. ++----------------------------------------------------------------------------*/ +#define SB_RTC_ADDR_PORT70 (NB_HT_IO_BASE_CPU+ 0x70) +#define SB_RTC_DATA_PORT71 (NB_HT_IO_BASE_CPU+ 0x71) +#define SB_RTC_ADDR_PORT72 (NB_HT_IO_BASE_CPU+ 0x72) +#define SB_RTC_DATA_PORT73 (NB_HT_IO_BASE_CPU+ 0x73) + + +/************ as_archppc.h ****************/ +/*----------------------------------------------------------------------------+ +| Schould be included only in assemble files. ++----------------------------------------------------------------------------*/ +//#ifdef __ASM__ + +/*----------------------------------------------------------------------------+ +| Register definitions and assembler specific definitions. ++----------------------------------------------------------------------------*/ +#ifdef __GNUC__ +#define new_section(name,attr) .section "name", "attr" +#define r0 0 +#define r1 1 +#define r2 2 +#define r3 3 +#define r4 4 +#define r5 5 +#define r6 6 +#define r7 7 +#define r8 8 +#define r9 9 +#define r10 10 +#define r11 11 +#define r12 12 +#define r13 13 +#define r14 14 +#define r15 15 +#define r16 16 +#define r17 17 +#define r18 18 +#define r19 19 +#define r20 20 +#define r21 21 +#define r22 22 +#define r23 23 +#define r24 24 +#define r25 25 +#define r26 26 +#define r27 27 +#define r28 28 +#define r29 29 +#define r30 30 +#define r31 31 +#define fr0 0 +#define fr1 1 +#define fr2 2 +#define fr3 3 +#define fr4 4 +#define fr5 5 +#define fr6 6 +#define fr7 7 +#define fr8 8 +#define fr9 9 +#define fr10 10 +#define fr11 11 +#define fr12 12 +#define fr13 13 +#define fr14 14 +#define fr15 15 +#define fr16 16 +#define fr17 17 +#define fr18 18 +#define fr19 19 +#define fr20 20 +#define fr21 21 +#define fr22 22 +#define fr23 23 +#define fr24 24 +#define fr25 25 +#define fr26 26 +#define fr27 27 +#define fr28 28 +#define fr29 29 +#define fr30 30 +#define fr31 31 +#endif +#ifdef __MW__ +#define new_section(name,attr) .section name, attr +#define r0 %r0 +#define r1 %r1 +#define r2 %r2 +#define r3 %r3 +#define r4 %r4 +#define r5 %r5 +#define r6 %r6 +#define r7 %r7 +#define r8 %r8 +#define r9 %r9 +#define r10 %r10 +#define r11 %r11 +#define r12 %r12 +#define r13 %r13 +#define r14 %r14 +#define r15 %r15 +#define r16 %r16 +#define r17 %r17 +#define r18 %r18 +#define r19 %r19 +#define r20 %r20 +#define r21 %r21 +#define r22 %r22 +#define r23 %r23 +#define r24 %r24 +#define r25 %r25 +#define r26 %r26 +#define r27 %r27 +#define r28 %r28 +#define r29 %r29 +#define r30 %r30 +#define r31 %r31 +#define fr0 %f0 +#define fr1 %f1 +#define fr2 %f2 +#define fr3 %f3 +#define fr4 %f4 +#define fr5 %f5 +#define fr6 %f6 +#define fr7 %f7 +#define fr8 %f8 +#define fr9 %f9 +#define fr10 %f10 +#define fr11 %f11 +#define fr12 %f12 +#define fr13 %f13 +#define fr14 %f14 +#define fr15 %f15 +#define fr16 %f16 +#define fr17 %f17 +#define fr18 %f18 +#define fr19 %f19 +#define fr20 %f20 +#define fr21 %f21 +#define fr22 %f22 +#define fr23 %f23 +#define fr24 %f24 +#define fr25 %f25 +#define fr26 %f26 +#define fr27 %f27 +#define fr28 %f28 +#define fr29 %f29 +#define fr30 %f30 +#define fr31 %f31 +#endif + +/*----------------------------------------------------------------------------+ +| Condition register defines. ++----------------------------------------------------------------------------*/ +#define cr0 0 +#define cr1 1 +#define cr2 2 +#define cr3 3 +#define cr4 4 +#define cr5 5 +#define cr6 6 +#define cr7 7 +#define cr0_0 0 +#define cr0_1 1 +#define cr0_2 2 +#define cr0_3 3 +#define cr1_0 4 +#define cr1_1 5 +#define cr1_2 6 +#define cr1_3 7 +#define cr2_0 8 +#define cr2_1 9 +#define cr2_2 10 +#define cr2_3 11 +#define cr3_0 12 +#define cr3_1 13 +#define cr3_2 14 +#define cr3_3 15 +#define cr4_0 16 +#define cr4_1 17 +#define cr4_2 18 +#define cr4_3 19 +#define cr5_0 20 +#define cr5_1 21 +#define cr5_2 22 +#define cr5_3 23 +#define cr6_0 24 +#define cr6_1 25 +#define cr6_2 26 +#define cr6_3 27 +#define cr6_sign 24 +#define cr6_inf 25 +#define cr6_zero 26 +#define cr6_NaN 27 +#define cr7_0 28 +#define cr7_1 29 +#define cr7_2 30 +#define cr7_3 31 +#define cr7_sign 28 +#define cr7_inf 29 +#define cr7_zero 30 +#define cr7_NaN 31 + +#define cr4_lt 16 +#define cr4_eq 18 +#define cr6_lt 24 +#define cr7_lt 28 + +/*----------------------------------------------------------------------------+ +| Basic PowerPC 32/64 bit instruction definitions and 32/64 bit defines. ++----------------------------------------------------------------------------*/ +#ifdef __PPC64__ +#define LOAD(rd,disp,ds) ld rd,disp(ds) +#define STORE(rs,disp,ra) std rs,disp(ra) +#define CMPI(cr,ra,si) cmpdi cr,ra,si +#define CMPL(cr,ra,rb) cmpld cr,ra,rb +#define GETTIMEBASEL(ra) mftb ra +#define TRACE_ENTRY_SIZE 16 +#define MULL(rt,ra,rb) mulld rt,ra,rb +#define RFI rfid +#else +#define LOAD(rd,disp,ds) lwz rd,disp(ds) +#define STORE(rs,disp,ra) stw rs,disp(ra) +#define CMPI(cr,ra,si) cmpwi cr,ra,si +#define CMPL(cr,ra,rb) cmplw cr,ra,rb +#define GETTIMEBASEL(ra) mfspr ra,tblr +#define TRACE_ENTRY_SIZE 12 +#define MULL(rt,ra,rb) mullw rt,ra,rb +#define RFI rfi +#endif + +/*----------------------------------------------------------------------------+ +| Macro for loading a 64 bit value into a register without using TOC and a +| TOC entry that has to be used when loading symbol address using TOC. ++----------------------------------------------------------------------------*/ +#ifdef __PPC64__ +#define LOAD_64BIT_VAL(ra,value) addis ra,r0,value@highest; \ + ori ra,ra,value@higher; \ + sldi ra,ra,32; \ + oris ra,ra,value@h; \ + ori ra,ra,value@l +#define TOC_ENTRY(name,symbol) .section ".toc","aw"; \ + name: .tc symbol[TC],symbol +#define GETSYMADDR(ra,sym,name) ld ra,name@toc(r2) +#else +#define TOC_ENTRY(name,symbol) +#define GETSYMADDR(ra,sym,name) addis ra,r0,sym@h;ori ra,ra,sym@l +#endif + +/*----------------------------------------------------------------------------+ +| Stack frame offsets. FP register area starts after back chain and LR save. +| Space to save non-volatile registers 16-31 starts after FP register area. +| Stack frame needs to be a multiple of 8 bytes for EABI. This is only used +| in 32-bit mode for floating point emulation functions. ++----------------------------------------------------------------------------*/ +#ifndef __PPC64__ +#define NUMB_SAVEREGS 16 +#define STACKSIZE ((NUMB_SAVEREGS* 4)+ 8) +#define SAVER_BASE 8 +#define SAVEREG(rn) stw r##rn,(SAVER_BASE+ (rn- 16)* 4)(r1) +#define RESTREG(rn) lwz r##rn,(SAVER_BASE+ (rn- 16)* 4)(r1) +#endif + +/*----------------------------------------------------------------------------+ +| Macros for function prolog/epilog, function call. ++----------------------------------------------------------------------------*/ +#ifdef __PPC64__ +#define function_prolog(fn) .section ".text"; \ + .align 2; \ + .globl fn; \ + .section ".opd","aw"; \ + .align 3; \ + fn:; \ + .quad .fn,.TOC.@tocbase,0; \ + .previous; \ + .size fn,24; \ + .globl .fn; \ + .fn: + +#define function_epilog(fn) .long 0; \ + .byte 0,12,0,0,0,0,0,0; \ + .type .fn,@function; \ + .size .fn,.-.fn + +#define data_global_prolog(dn) .section ".toc","aw"; \ + .tc dn[TC],dn; \ + .section ".data"; \ + .align 3; \ + .globl dn; \ + dn: + +#define data_global_epilog(dn) .type dn,@object; \ + .size dn,.-dn + +#define data_prolog(dn) .section ".toc","aw"; \ + .tc dn[TC],dn; \ + .section ".data"; \ + .align 3; \ + dn: + +#define data_epilog(data_name) .type dn,@object; \ + .size dn,.-dn + +#define function_call(func_name) bl .func_name + +#else +#define function_nos_prolog(func_name) .align 2; \ + .globl func_name; \ + func_name: + +#define function_prolog(func_name) .text; \ + .align 2; \ + .globl func_name; \ + func_name: + +#define function_epilog(func_name) .type func_name,@function; \ + .size func_name,.-func_name + +#define data_global_prolog(data_name) .data; \ + .align 2; \ + .globl data_name; \ + data_name: + +#define data_global_epilog(data_name) .type data_name,@object; \ + .size data_name,.-data_name + +#define data_prolog(data_name) .data; \ + .align 2; \ + data_name: + +#define data_epilog(data_name) .type data_name,@object; \ + .size data_name,.-data_name + +#define function_call(func_name) bl func_name + +#endif + +/*----------------------------------------------------------------------------+ +| EABI and 64-bit API stack frame definition. ++----------------------------------------------------------------------------*/ +#ifdef __PPC64__ +#define stack_frame_min 112 +#define stack_frame_bc 0 +#define stack_frame_lr 16 +#define stack_neg_off 288 +#else +#define stack_frame_min 8 +#define stack_frame_bc 0 +#define stack_frame_lr 4 +#define stack_neg_off 0 +#endif + +/*----------------------------------------------------------------------------+ +| Size of the context register. ++----------------------------------------------------------------------------*/ +#ifdef __PPC64__ +#define stack_reg_image_size 328 +#define stack_reg_img_s_new 328 +#define stack_reg_s_spr 72 +#else +#define stack_reg_image_size 160 +#define stack_reg_img_s_new 168 +#define stack_reg_s_spr 40 +#endif + +/*----------------------------------------------------------------------------+ +| "dlmzb" instruction is not supported by the GNU assembler. On 7XX +| processorsdlmzb instruction does not exist. In that case the instruction +| is emulated. The emulated unstruction does not set CR[CR0] SO (overflow). ++----------------------------------------------------------------------------*/ +#if ! defined __PPC7XX__ && ! defined __PPC64__ +#define DLMZBDOT(ra,rs,rb,lab,rt) .long 0x7c00009d|\ + (rs<<21)|(ra<<16)|(rb<<11) + +#define DLMZBNDOT(ra,rs,rb,lab,rt) .long 0x7c00009c|\ + (rs<<21)|(ra<<16)|(rb<<11) +#else +#define DLMZBDOT(ra,rs,rb,lab,rt) addi ra,r0,0x0001;\ + rlwinm. rt,rs,0,0,7;\ + beq lab##end1;\ + addi ra,r0,0x0002;\ + rlwinm. rt,rs,0,8,15;\ + beq lab##end1;\ + addi ra,r0,0x0003;\ + rlwinm. rt,rs,0,16,23;\ + beq lab##end1;\ + addi ra,r0,0x0004;\ + rlwinm. rt,rs,0,24,31;\ + beq lab##end1;\ + addi ra,r0,0x0005;\ + rlwinm. rt,rb,0,0,7;\ + beq lab##end2;\ + addi ra,r0,0x0006;\ + rlwinm. rt,rb,0,8,15;\ + beq lab##end2;\ + addi ra,r0,0x0007;\ + rlwinm. rt,rb,0,16,23;\ + beq lab##end2;\ + addi ra,r0,0x0008;\ + rlwinm. rt,rb,0,24,31;\ + beq lab##end2;\ + addis rt,r0,0x2000;\ + mtcrf 0x80,rt;\ + b lab##fin;\ + lab##end1:;\ + addis rt,r0,0x4000;\ + mtcrf 0x80,rt;\ + b lab##fin;\ + lab##end2:;\ + addis rt,r0,0x8000;\ + mtcrf 0x80,rt;\ + lab##fin:;\ + mfspr rt,xer_reg;\ + rlwinm rt,rt,0,0,24;\ + or rt,rt,ra;\ + mtspr xer_reg,rt + +#define DLMZBNDOT(ra,rs,rb,lab,rt) addi ra,r0,0x0001;\ + rlwinm. rt,rs,0,0,7;\ + beq lab##end;\ + addi ra,r0,0x0002;\ + rlwinm. rt,rs,0,8,15;\ + beq lab##end;\ + addi ra,r0,0x0003;\ + rlwinm. rt,rs,0,16,23;\ + beq lab##end;\ + addi ra,r0,0x0004;\ + rlwinm. rt,rs,0,24,31;\ + beq lab##end;\ + addi ra,r0,0x0005;\ + rlwinm. rt,rb,0,0,7;\ + beq lab##end;\ + addi ra,r0,0x0006;\ + rlwinm. rt,rb,0,8,15;\ + beq lab##end;\ + addi ra,r0,0x0007;\ + rlwinm. rt,rb,0,16,23;\ + beq lab##end;\ + addi ra,r0,0x0008;\ + rlwinm. rt,rb,0,24,31;\ + lab##end:;\ + mfspr rt,xer_reg;\ + rlwinm rt,rt,0,0,24;\ + or rt,rt,ra;\ + mtspr xer_reg,rt +#endif + +/*----------------------------------------------------------------------------+ +| Following instructions are not available in Book E mode of the GNU assembler. ++----------------------------------------------------------------------------*/ +#ifdef __PPC64__ +#define TLBIEL(rb) .long 0x7C000000|\ + (rb<<11)|(274<<1) +#define HRFID() .long 0x4C000000|\ + (274<<1) +#else +#define DCCCI(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(454<<1) + +#define ICCCI(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(966<<1) + +#define DCREAD(rt,ra,rb) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(rb<<11)|(486<<1) + +#define ICREAD(ra,rb) .long 0x7c000000|\ + (ra<<16)|(rb<<11)|(998<<1) + +#define TLBSX(rt,ra,rb) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) + +#define TLBWE(rs,ra,ws) .long 0x7c000000|\ + (rs<<21)|(ra<<16)|(ws<<11)|(978<<1) + +#define TLBRE(rt,ra,ws) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) + +#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\ + (rt<<21)|(ra<<16)|(rb<<11)|(914<<1) + +#define MSYNC .long 0x7c000000|\ + (598<<1) + +#define MBAR .long 0x7c000000|\ + (854<<1) +#endif + +/*----------------------------------------------------------------------------+ +| Special Purpose Registers. Xer, lr, ctr, srr0, srr1, sprg0, sprg1, sprg2, +| sprg3, pvr, tbl (read), tlu (read) registers. ++----------------------------------------------------------------------------*/ +#define xer_reg 0x001 +#define lr_reg 0x008 +#define ctr 0x009 +#define srr0 0x01a +#define srr1 0x01b +#define sprg0 0x110 +#define sprg1 0x111 +#define sprg2 0x112 +#define sprg3 0x113 +#define pvr 0x11f +#define tblr 0x10c +#define tbur 0x10d + +//#endif //__ASM__ + +/*----------------------------------------------------------------------------+ +| Same as above for the C code. ++----------------------------------------------------------------------------*/ +#define SPR_SRR0 0x01a +#define SPR_SRR1 0x01b +#define SPR_SPRG0 0x110 +#define SPR_SPRG1 0x111 +#define SPR_SPRG2 0x112 +#define SPR_SPRG3 0x113 +#define SPR_PVR 0x11f +#define SPR_TBLR 0x10c +#define SPR_TBUR 0x10d + +/*----------------------------------------------------------------------------+ +| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1. ++----------------------------------------------------------------------------*/ +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_FE1 0x00000100 + + +/************ as_archppc970.h ****************/ +/*----------------------------------------------------------------------------+ +| PVR value. ++----------------------------------------------------------------------------*/ +#define PVR_970_DD1 0x00391100 +#define PVR_970FX_DD2 0x003C0200 +#define PVR_970FX_DD2_1 0x003C0201 +#define PVR_970FX_DD3 0x003C0300 + +/*----------------------------------------------------------------------------+ +| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64) +| sprg0 (64), sprg1 (64), sprg2 (64), sprg3 (64), pvr (32) tblr (64), tbur (32) +| registers are defined in as_archppc.h. ++----------------------------------------------------------------------------*/ +#define SPR_ACCR 0x001D /* 64-bit read/write $*/ +#define SPR_ASR 0x0118 /* 64-bit read/write, write hypervisor only */ +#define SPR_DABR 0x03F5 /* 64-bit read/write, write hypervisor only */ +#define SPR_DABRX 0x03F7 /* 64-bit read/write, write hypervisor only */ +#define SPR_DAR 0x0013 /* 64-bit read/write */ +#define SPR_DEC 0x0016 /* 32-bit read/write */ +#define SPR_DSISR 0x0012 /* 32-bit read/write */ +#define SPR_HDEC 0x0136 /* 64-bit read/write, write hypervisor only */ +#define SPR_HID0 0x03F0 /* 64-bit read/write, write hypervisor only */ +#define SPR_HID1 0x03F1 /* 64-bit read/write, write hypervisor only */ +#define SPR_HID4 0x03F4 /* 64-bit read/write, write hypervisor only */ +#define SPR_HID5 0x03F6 /* 64-bit read/write, write hypervisor only */ +#define SPR_HIOR 0x0137 /* 64-bit read/write */ +#define SPR_HSPRG0 0x0130 /* 64-bit read/write, write hypervisor only */ +#define SPR_HSPRG1 0x0131 /* 64-bit read/write, write hypervisor only */ +#define SPR_HSRR0 0x013A /* 64-bit read/write, write hypervisor only */ +#define SPR_HSRR1 0x013B /* 64-bit read/write, write hypervisor only */ +#define SPR_IMC 0x030F /* 64-bit read/write */ +#define SPR_MMCR0 0x031B /* 64-bit read/write */ +#define SPR_MMCR1 0x031E /* 64-bit read/write */ +#define SPR_MMCRA 0x0312 /* 64-bit read/write */ +#define SPR_PIR 0x03FF /* 32-bit read */ +#define SPR_PMC1 0x0313 /* 32-bit read/write */ +#define SPR_PMC2 0x0314 /* 32-bit read/write */ +#define SPR_PMC3 0x0315 /* 32-bit read/write */ +#define SPR_PMC4 0x0316 /* 32-bit read/write */ +#define SPR_PMC5 0x0317 /* 32-bit read/write */ +#define SPR_PMC6 0x0318 /* 32-bit read/write */ +#define SPR_PMC7 0x0319 /* 32-bit read/write */ +#define SPR_PMC8 0x031A /* 32-bit read/write */ +#define SPR_SCOMC 0x0114 /* 64-bit read/write, write hypervisor only */ +#define SPR_SCOMD 0x0115 /* 64-bit read/write, write hypervisor only */ +#define SPR_SDAR 0x031D /* 64-bit read/write */ +#define SPR_SDR1 0x0019 /* 64-bit read/write, write hypervisor only */ +#define SPR_SIAR 0x031C /* 64-bit read/write */ +#define SPR_TBL_WRITE 0x011C /* 32-bit write */ +#define SPR_TBU_WRITE 0x011D /* 32-bit write */ +#define SPR_TRACE 0x03FE /* 64-bit read $*/ +#define SPR_TRIG0 0x03D0 /* 64-bit write */ +#define SPR_TRIG1 0x03D1 /* 64-bit write */ +#define SPR_TRIG2 0x03D2 /* 64-bit write */ +#define SPR_VRSAVE 0x0100 /* 64-bit read/write $*/ + +/*----------------------------------------------------------------------------+ +| Vector status and control register is accessed using the mfvscr and mtvscr +| instructions. ++----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------+ +| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1, +| register bits are defined in as_archppc.h. This is a 64-bit register. ++----------------------------------------------------------------------------*/ +#define MSR_SF 0x8000000000000000 /* 64/32 bit mode indicator */ +#define MSR_HV 0x1000000000000000 /* hypervisor mode */ +#define MSR_VMX 0x0000000002000000 /* vmx unit available */ +#define MSR_POW 0x0000000000040000 /* power management enable */ +#define MSR_SE 0x0000000000000400 /* single step */ +#define MSR_BE 0x0000000000000200 /* branch trace */ +#define MSR_IS 0x0000000000000020 /* instruction address space */ +#define MSR_DS 0x0000000000000010 /* data address space */ +#define MSR_PM 0x0000000000000004 /* performance monitor */ +#define MSR_RI 0x0000000000000002 /* recoverable interrupt */ + +/*----------------------------------------------------------------------------+ +| HID0 bits. ++----------------------------------------------------------------------------*/ +#define HID0_ONEPPC 0x8000000000000000 +#define HID0_SINGLE 0x4000000000000000 +#define HID0_ISYNC_SC 0x2000000000000000 +#define HID0_SERIAL_G 0x1000000000000000 +#define HID0_DEEP_NAP 0x0100000000000000 +#define HID0_NAP 0x0040000000000000 +#define HID0_DPM 0x0010000000000000 +#define HID0_TR_GR 0x0004000000000000 +#define HID0_TR_DIS 0x0002000000000000 +#define HID0_NHR 0x0001000000000000 +#define HID0_INORDER 0x0000800000000000 +#define HID0_ENH_TR 0x0000400000000000 +#define HID0_TB_CTRL 0x0000200000000000 +#define HID0_EXT_TB_EN 0x0000100000000000 +#define HID0_CIABR_EN 0x0000020000000000 +#define HID0_HDEC_EN 0x0000010000000000 +#define HID0_EB_THERM 0x0000008000000000 +#define HID0_EN_ATTN 0x0000000100000000 +#define HID0_EN_MAC 0x0000000080000000 + +/*----------------------------------------------------------------------------+ +| HID1 bits. ++----------------------------------------------------------------------------*/ +#define HID1_BHT_PM 0xE000000000000000 +#define HID1_BHT_STATIC 0x0000000000000000 +#define HID1_BHT_GLOBAL 0x4000000000000000 +#define HID1_BHT_LOCAL 0x8000000000000000 +#define HID1_BHT_GL_LO 0xC000000000000000 +#define HID1_BHT_GL_CO 0x6000000000000000 +#define HID1_BHT_FULL 0xE000000000000000 +#define HID1_EN_LS 0x1000000000000000 +#define HID1_EN_CC 0x0800000000000000 +#define HID1_EN_IC 0x0400000000000000 +#define HID1_PF_MASK 0x0180000000000000 +#define HID1_PF_NSA 0x0080000000000000 +#define HID1_PF_NSA_P 0x0100000000000000 +#define HID1_PF_DIS 0x0180000000000000 +#define HID1_EN_ICBI 0x0040000000000000 +#define HID1_EN_IF_CACH 0x0020000000000000 +#define HID1_EN_IC_REC 0x0010000000000000 +#define HID1_EN_ID_REC 0x0008000000000000 +#define HID1_EN_ER_REC 0x0004000000000000 +#define HID1_IC_PE 0x0002000000000000 +#define HID1_ICD0_PE 0x0001000000000000 +#define HID1_ICD1_PE 0x0000800000000000 +#define HID1_IER_PE 0x0000400000000000 +#define HID1_EN_SP_ITW 0x0000200000000000 +#define HID1_S_CHICKEN 0x0000100000000000 + +/*----------------------------------------------------------------------------+ +| HID4 bits. ++----------------------------------------------------------------------------*/ +#define HID4_LPES0 0x8000000000000000 +#define HID4_RMLR12_MSK 0x6000000000000000 +#define HID4_LPID25_MSK 0x1E00000000000000 +#define HID4_RMOR_MASK 0x01FFFE0000000000 +#define HID4_RM_CI 0x0000010000000000 +#define HID4_FORCE_AI 0x0000008000000000 +#define HID4_DIS_PERF 0x0000004000000000 +#define HID4_RES_PERF 0x0000002000000000 +#define HID4_EN_SP_DTW 0x0000001000000000 +#define HID4_L1DC_FLSH 0x0000000800000000 +#define HID4_D_DERAT_P1 0x0000000400000000 +#define HID4_D_DERAT_P2 0x0000000200000000 +#define HID4_D_DERAT_G 0x0000000100000000 +#define HID4_D_DERAT_S1 0x0000000040000000 +#define HID4_D_DERAT_S2 0x0000000080000000 +#define HID4_DC_TP_S1 0x0000000020000000 +#define HID4_DC_TP_S2 0x0000000010000000 +#define HID4_DC_TP_GEN 0x0000000008000000 +#define HID4_DC_SET1 0x0000000004000000 +#define HID4_DC_SET2 0x0000000002000000 +#define HID4_DC_DP_S1 0x0000000001000000 +#define HID4_DC_DP_S2 0x0000000000800000 +#define HID4_DC_DP_GEN 0x0000000000400000 +#define HID4_R_TAG1P_CH 0x0000000000200000 +#define HID4_R_TAG2P_CH 0x0000000000100000 +#define HID4_TLB_PC1 0x0000000000080000 +#define HID4_TLB_PC2 0x0000000000040000 +#define HID4_TLB_PC3 0x0000000000020000 +#define HID4_TLB_PC4 0x0000000000010000 +#define HID4_TLB_P_GEN 0x0000000000008000 +#define HID4_TLB_SET1 0x0000000000003800 +#define HID4_TLB_SET2 0x0000000000005800 +#define HID4_TLB_SET3 0x0000000000006800 +#define HID4_TLB_SET4 0x0000000000007000 +#define HID4_DIS_SLBPC 0x0000000000000400 +#define HID4_DIS_SLBPG 0x0000000000000200 +#define HID4_MCK_INJ 0x0000000000000100 +#define HID4_DIS_STFWD 0x0000000000000080 +#define HID4_LPES1 0x0000000000000040 +#define HID4_RMLR0_MSK 0x0000000000000020 +#define HID4_DIS_SPLARX 0x0000000000000008 +#define HID4_LP_PG_EN 0x0000000000000004 +#define HID4_LPID01_MSK 0x0000000000000003 + +/*----------------------------------------------------------------------------+ +| HID5 bits. ++----------------------------------------------------------------------------*/ +#define HID5_HRMOR_MASK 0x00000000FFFF0000 +#define HID5_DC_MCK 0x0000000000002000 +#define HID5_DIS_PWRSAV 0x0000000000001000 +#define HID5_FORCE_G 0x0000000000000800 +#define HID5_DC_REPL 0x0000000000000400 +#define HID5_HWR_STMS 0x0000000000000200 +#define HID5_DST_NOOP 0x0000000000000100 +#define HID5_DCBZ_SIZE 0x0000000000000080 +#define HID5_DCBZ32_ILL 0x0000000000000040 +#define HID5_TLB_MAP 0x0000000000000020 +#define HID5_IMQ_PORT 0x0000000000000010 +#define HID5_LMP_SIZE0 0x0000000000000008 +#define HID5_DPFLOOD 0x0000000000000004 +#define HID5_TCH_NOP 0x0000000000000002 +#define HID5_LMP_SIZE1 0x0000000000000001 + +/*----------------------------------------------------------------------------+ +| Specific SRR1 bit definitions for Machine Check. ++----------------------------------------------------------------------------*/ +#define SRR1_IFU_UNREC 0x0000000000200000 +#define SRR1_LOAD_STORE 0x0000000000100000 +#define SRR1_SLB_PARITY 0x0000000000040000 +#define SRR1_TLB_PARITY 0x0000000000080000 +#define SRR1_ITLB_RELOA 0x00000000000C0000 +#define SRR1_RI 0x0000000000000002 + +#endif /* _ppc970_h_ */ diff --git a/src/arch/ppc/include/ppc970lib.h b/src/arch/ppc/include/ppc970lib.h new file mode 100755 index 0000000000..a7f3d2fdd0 --- /dev/null +++ b/src/arch/ppc/include/ppc970lib.h @@ -0,0 +1,279 @@ +#ifndef _ppc970lib_h_ +#define _ppc970lib_h_ + +/*----------------------------------------------------------------------------+ +| Time base structure. ++----------------------------------------------------------------------------*/ +typedef struct tb { + unsigned long tb_all; +} tb_t; + +/*----------------------------------------------------------------------------+ +| 970FX specific ppc prototypes. ++----------------------------------------------------------------------------*/ +void ppcMfvscr( + void ); + +void ppcMtvscr( + void ); + +int ppcMfvr( + unsigned int reg_num, + unsigned long *data_msb, + unsigned long *data_lsb ); + +int ppcMtvr( + unsigned int reg_num, + unsigned long data_msb, + unsigned long data_lsb ); + +void ppcLvxl( + unsigned int reg_num, + void *addr ); + +void ppcStvx( + unsigned int reg_num, + void *addr ); + +unsigned long ppcMflr( + void ); + +unsigned char inbyte( + unsigned long addr ); + +void outbyte( + unsigned long addr, + unsigned int data ); + +unsigned short inhalf( + unsigned long addr ); + +void outhalf( + unsigned long addr, + unsigned int data ); + +unsigned short inhalf_brx( + unsigned long addr ); + +void outhalf_brx( + unsigned long addr, + unsigned int data ); + +unsigned long inword( + unsigned long addr ); + +void outword( + unsigned long addr, + unsigned long data ); + +unsigned int inint( + unsigned long addr ); + +void outint( + unsigned long addr, + unsigned int data ); + +unsigned int inint_brx( + unsigned long addr ); + +void outint_brx( + unsigned long addr, + unsigned int data ); + +void ppcDflush( + void ); + +void ppcDcbz_area( + unsigned long addr, + unsigned long len ); + +unsigned long ppcTlbsync( + void ); + +unsigned long ppcTlbie( + unsigned long vaddr, + int large_page ); + +void ppcTlbiel( + unsigned long vaddr ); + +void ppcSlbie( + unsigned long rb ); + +void ppcSlbia( + void ); + +void ppcSlbmte( + unsigned long rs, + unsigned long rb ); + +unsigned long ppcSlbmfev( + int index ); + +unsigned long ppcSlbmfee( + int index ); + +void ppcAbend( + void ); + +unsigned long ppcAndMsr( + unsigned long value ); + +unsigned int ppcCntlzw( + unsigned int value ); + +unsigned int ppcCntlzd( + unsigned long value ); + +void ppcDcbf( + void *addr ); + +void ppcDcbst( + void *addr ); + +void ppcDcbz( + void *addr ); + +void ppcHalt( + void ); + +void ppcIcbi( + void *addr ); + +void ppcIsync( + void ); + +unsigned long ppcMfgpr1( + void ); + +unsigned long ppcMfgpr2( + void ); + +void ppcMtmsr( + unsigned long msr_value ); + +unsigned long ppcMfmsr( + void ); + +unsigned long ppcOrMsr( + unsigned long value ); + +void ppcSync( + void ); + +void ppcLwsync( + void ); + +void ppcPtesync( + void ); + +void ppcEieio( + void ); + +void ppcTestandset( + unsigned long addr, + unsigned long value ); + +unsigned long ppcMfscom( + unsigned int scom_num ); + +void ppcMtscom( + unsigned int scom_num, + unsigned long scom_data ); + +/*----------------------------------------------------------------------------+ +| 970FX SPR's. ++----------------------------------------------------------------------------*/ +void ppcMthid0( + unsigned long data ); + +void ppcMthid1( + unsigned long data ); + +void ppcMthid4( + unsigned long data ); + +void ppcMthid5( + unsigned long data ); + +void ppcMftb( + tb_t *clock_data ); + +void ppcMttb( + tb_t *clock_data ); + +void ppcMtspr_any( + unsigned int spr_num, + unsigned long value ); + +unsigned long ppcMfspr_any( + unsigned int spr_num ); + +/*----------------------------------------------------------------------------+ +| Additional functions required by debug connection. ++----------------------------------------------------------------------------*/ +int ppcCachelinesize( + void ); + +unsigned long ppcProcid( + void ); + +void ppcMtmmucr( + unsigned long data ); + +void ppcMttlb1( + unsigned long index, + unsigned long value ); + +void ppcMttlb2( + unsigned long index, + unsigned long value ); + +void ppcMttlb3( + unsigned long index, + unsigned long value ); + +unsigned long ppcMftlb1( + unsigned long index ); + +unsigned long ppcMftlb2( + unsigned long index ); + +unsigned long ppcMftlb3( + unsigned long index ); + +unsigned long ppcMfmmucr( + void ); + +unsigned long ppcMfdcr_any( + unsigned long dcr_num ); + +unsigned long ppcMfspr_any_name( + char *name, + unsigned long *value_msb ); + +void ppcMtdcr_any( + unsigned long dcr_num, + unsigned long value ); + +void ppcMtspr_any_name( + char *name, + unsigned long value_lsb, + unsigned long value_msb ); + +int ppcIstrap( + void ); + +unsigned long p_ptegg( + int lp, + unsigned long ea, + unsigned long sdr1, + unsigned long vsid ); + +unsigned long s_ptegg( + int lp, + unsigned long ea, + unsigned long sdr1, + unsigned long vsid ); + +#endif /* _ppc970lib_h_ */ diff --git a/src/arch/ppc/init/ldscript.lb b/src/arch/ppc/init/ldscript.lb index 63a32b735d..0afc563b50 100644 --- a/src/arch/ppc/init/ldscript.lb +++ b/src/arch/ppc/init/ldscript.lb @@ -1,94 +1,372 @@ -/* - * Memory map: - * - * _ROMBASE : start of ROM - * _RESET : reset vector (may be at top of ROM) - * _EXCEPTIONS_VECTORS : exception table - * - * _ROMSTART : linuxbios text - * : payload text - * - * _RAMBASE : address to copy payload - */ - -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - * Re-rewritten by Greg Watson for PPC - */ - -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ - -OUTPUT_FORMAT("elf32-powerpc") -ENTRY(_start) - -TARGET(binary) -INPUT(linuxbios_ram.rom) +/*----------------------------------------------------------------------------+ +| Memory layout. RAM length is referenced again in __heap_size variable +| definition. ++----------------------------------------------------------------------------*/ +MEMORY +{ + RAM_VECT (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + RAM (rwx) : ORIGIN = 0x00010000, LENGTH = 0x003F0000 + ROM_INIT (r x) : ORIGIN = 0xFFF00000, LENGTH = 0x00002000 + ROM (r x) : ORIGIN = 0xFFF02000, LENGTH = 0x000FE000 +} + +/*----------------------------------------------------------------------------+ +| Sections originally taken from default GNU LD script. ++----------------------------------------------------------------------------*/ SECTIONS { - /* - * Absolute location of base of ROM - */ - . = _ROMBASE; - - /* - * Absolute location of reset vector. This may actually be at the - * the top of ROM. - */ - . = _RESET; - .reset . : { - *(.rom.reset); - . = ALIGN(16); - } - - /* - * Absolute location of exception vector table. - */ - . = _EXCEPTION_VECTORS; - .exception_vectors . : { - *(.rom.exception_vectors); - . = ALIGN(16); - } - - /* - * Absolute location of LinuxBIOS initialization code in ROM. - */ - . = _ROMSTART; - .rom . : { - _rom = .; - *(.rom.text); - *(.text); - *(.rom.data); - *(.rodata); - *(EXCLUDE_FILE(linuxbios_ram.rom) .data); - . = ALIGN(16); - _erom = .; - } - _lrom = LOADADDR(.rom); - _elrom = LOADADDR(.rom) + SIZEOF(.rom); - - /* - * Ram is the LinuxBIOS code that runs from RAM. - */ - .ram . : { - _ram = . ; - linuxbios_ram.rom(*) - _eram = . ; - } - - /* - * Absolute location of where LinuxBIOS will be relocated in RAM. - */ - _iseg = _RAMBASE; - _eiseg = _iseg + SIZEOF(.ram); - _liseg = _ram; - _eliseg = _eram; - - /DISCARD/ : { - *(.comment) - *(.note) - } + + /*-------------------------------------------------------------------------+ + | Create dummy section. We need to do this so that the __stext symbol is + | set correctly. + +-------------------------------------------------------------------------*/ + .dummyt : + { + LONG(0x00000000) + } > RAM + + /*-------------------------------------------------------------------------+ + | Create variable holding the value of the start of the text. + +-------------------------------------------------------------------------*/ + __stext = . - SIZEOF(.dummyt); + + .hash : + { + *(.hash) + } > RAM + + .dynsym : + { + *(.dynsym) + } > RAM + + .dynstr : + { + *(.dynstr) + } > RAM + + .rel.init : + { + *(.rel.init) + } > RAM + + .rela.init : + { + *(.rela.init) + } > RAM + + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t.*) + } > RAM + + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t.*) + } > RAM + + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r.*) + } > RAM + + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r.*) + } > RAM + + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d.*) + } > RAM + + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d.*) + } > RAM + + .rel.sdata : + { + *(.rel.sdata) + *(.rel.sdata.*) + *(.rel.gnu.linkonce.s.*) + } > RAM + + .rela.sdata : + { + *(.rela.sdata) + *(.rela.sdata.*) + *(.rela.gnu.linkonce.s.*) + } > RAM + + .rel.sbss : + { + *(.rel.sbss) + *(.rel.sbss.*) + *(.rel.gnu.linkonce.sb.*) + } > RAM + + .rela.sbss : + { + *(.rela.sbss) + *(.rela.sbss.*) + *(.rel.gnu.linkonce.sb.*) + } > RAM + + .rel.sdata2 : + { + *(.rel.sdata2) + *(.rel.sdata2.*) + *(.rel.gnu.linkonce.s2.*) + } > RAM + + .rela.sdata2 : + { + *(.rela.sdata2) + *(.rela.sdata2.*) + *(.rela.gnu.linkonce.s2.*) + } > RAM + + .rel.sbss2 : + { + *(.rel.sbss2) + *(.rel.sbss2.*) + *(.rel.gnu.linkonce.sb2.*) + } > RAM + + .rela.sbss2 : + { + *(.rela.sbss2) + *(.rela.sbss2.*) + *(.rela.gnu.linkonce.sb2.*) + } > RAM + + .rel.bss : + { + *(.rel.bss) + *(.rel.bss.*) + *(.rel.gnu.linkonce.b.*) + } > RAM + + .rela.bss : + { + *(.rela.bss) + *(.rela.bss.*) + *(.rela.gnu.linkonce.b.*) + } > RAM + + .rel.plt : + { + *(.rel.plt) + } > RAM + + .rela.plt : + { + *(.rela.plt) + } > RAM + + /*-------------------------------------------------------------------------+ + | Keep the .init sections even if they are not referenced. Fill in the + | space (if any) in the .init serctions with 0. + +-------------------------------------------------------------------------*/ + .text : + { + *(.text) + *(.text.*) + *(.stub) + *(.gnu.warning) + *(.gnu.linkonce.t.*) + } > RAM = 0 + + /*-------------------------------------------------------------------------+ + | Create variable holding the value of the end of the text. + +-------------------------------------------------------------------------*/ + __etext = .; + + /*-------------------------------------------------------------------------+ + | Create variable holding the value of the start of the data. + +-------------------------------------------------------------------------*/ + __sdata = .; + + .rodata : + { + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + } > RAM + + .rodata1 : + { + *(.rodata1) + } > RAM + + .sdata2 : + { + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + } > RAM + + .sbss2 : + { + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > RAM + + /*-------------------------------------------------------------------------+ + | Align data to word boundary. + +-------------------------------------------------------------------------*/ + . = ALIGN(4); + + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + } > RAM + + .toc : + { + *(.toc) + *(.toc.*) + } > RAM + + .opd : + { + *(.opd) + *(.opd.*) + } > RAM + + .data1 : + { + *(.data1) + } > RAM + + .eh_frame : + { + KEEP(*(.eh_frame)) + } > RAM + + .fixup : + { + *(.fixup) + } > RAM + + .dynamic : + { + *(.dynamic) + } > RAM + + /*-------------------------------------------------------------------------+ + | We want the small data sections together, so single-instruction offsets + | can access them all, and initialized data all before uninitialized, so + | we can shorten the on-disk segment size. + +-------------------------------------------------------------------------*/ + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } > RAM + + /*-------------------------------------------------------------------------+ + | Create variable holding the value of the end of the data. + +-------------------------------------------------------------------------*/ + __edata = .; + + /*-------------------------------------------------------------------------+ + | Create variable holding the value of the start of the bss. + +-------------------------------------------------------------------------*/ + __sbss = .; + + .sbss : + { + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > RAM + + .plt : + { + *(.plt) + } > RAM + + /*-------------------------------------------------------------------------+ + | Common symbols are placed in the BSS section. + +-------------------------------------------------------------------------*/ + .bss : + { + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + } > RAM + + /*-------------------------------------------------------------------------+ + | Align so that the bss size and __ebss are word aligned. + +-------------------------------------------------------------------------*/ + . = ALIGN(4); + + /*-------------------------------------------------------------------------+ + | Create variable holding the value of the end of the bss. + +-------------------------------------------------------------------------*/ + __ebss = .; + + /*-------------------------------------------------------------------------+ + | Create variables describing the heap. The value "0x3F0000" must be + | equal to RAM length. + +-------------------------------------------------------------------------*/ + __heap_start = .; + __heap_size = 0x3F0000 + ADDR(.dummyt) - .; + + /*-------------------------------------------------------------------------+ + | Stabs. Symbols in the following sections are relative to the beginning + | of the section so we begin them at 0. + +-------------------------------------------------------------------------*/ + .stab 0 : + { + *(.stab) + } + + .stabstr 0 : + { + *(.stabstr) + } + + .stab.excl 0 : + { + *(.stab.excl) + } + + .stab.exclstr 0 : + { + *(.stab.exclstr) + } + + .stab.index 0 : + { + *(.stab.index) + } + + .stab.indexstr 0 : + { + *(.stab.indexstr) + } + } diff --git a/src/arch/ppc/init/ppc_main.c b/src/arch/ppc/init/ppc_main.c index 4dd4487ae8..80674d295e 100644 --- a/src/arch/ppc/init/ppc_main.c +++ b/src/arch/ppc/init/ppc_main.c @@ -6,11 +6,13 @@ #include #include +#ifndef __PPC64__ extern unsigned _iseg[]; extern unsigned _liseg[]; extern unsigned _eliseg[]; void (*payload)(void) = (void (*)(void))_iseg; +#endif /* * At this point we're running out of flash with our @@ -21,7 +23,9 @@ void (*payload)(void) = (void (*)(void))_iseg; * - start hardwaremain() which does remainder of setup */ +#ifndef __PPC64__ extern void flush_dcache(void); +#endif void ppc_main(void) { @@ -43,6 +47,7 @@ void ppc_main(void) */ board_init2(); +#ifndef __PPC64__ /* * Flush cache now that memory is enabled. */ @@ -59,6 +64,7 @@ void ppc_main(void) } payload(); +#endif /* NOT REACHED */ } diff --git a/src/arch/ppc/lib/c_start.S b/src/arch/ppc/lib/c_start.S index d0d2a8f3d7..e7ae2a20c9 100644 --- a/src/arch/ppc/lib/c_start.S +++ b/src/arch/ppc/lib/c_start.S @@ -7,6 +7,7 @@ * configuring the machine. */ +#ifndef __PPC64__ #define ASM #include "ppcreg.h" #include @@ -109,3 +110,5 @@ __DTOR_LIST__: .globl __DTOR_END__ __DTOR_END__: blr + +#endif diff --git a/src/arch/ppc/lib/div64.S b/src/arch/ppc/lib/div64.S index 48047747e0..1cc4e7c7bf 100644 --- a/src/arch/ppc/lib/div64.S +++ b/src/arch/ppc/lib/div64.S @@ -15,8 +15,13 @@ */ #include +#ifndef __PPC64__ .globl __div64_32 __div64_32: +#else + .globl .__div64_32 +.__div64_32: +#endif lwz r5,0(r3) # get the dividend into r5/r6 lwz r6,4(r3) cmplw r5,r4 diff --git a/src/arch/ppc/lib/timebase.S b/src/arch/ppc/lib/timebase.S index 9e0b2a9290..43023c0418 100644 --- a/src/arch/ppc/lib/timebase.S +++ b/src/arch/ppc/lib/timebase.S @@ -28,8 +28,13 @@ /* * unsigned long long _get_ticks(void); */ +#ifndef __PPC64__ .globl _get_ticks _get_ticks: +#else + .globl ._get_ticks +._get_ticks: +#endif 1: mftbu r3 mftb r4 mftbu r5 @@ -40,17 +45,30 @@ _get_ticks: /* * Delay for a number of ticks */ +#ifndef __PPC64__ .globl _wait_ticks _wait_ticks: +#else + .globl ._wait_ticks +._wait_ticks: +#endif mflr r8 /* save link register */ mr r7, r3 /* save tick count */ +#ifndef __PPC64__ bl _get_ticks /* Get start time */ +#else + bl ._get_ticks /* Get start time */ +#endif /* Calculate end time */ addc r7, r4, r7 /* Compute end time lower */ addze r6, r3 /* and end time upper */ +#ifndef __PPC64__ 1: bl _get_ticks /* Get current time */ +#else +1: bl ._get_ticks /* Get current time */ +#endif subfc r4, r4, r7 /* Subtract current time from end time */ subfe. r3, r3, r6 bge 1b /* Loop until time expired */ diff --git a/src/cpu/ppc/ppc970/Config.lb b/src/cpu/ppc/ppc970/Config.lb index 60da7f2b71..3c6a3bc247 100644 --- a/src/cpu/ppc/ppc970/Config.lb +++ b/src/cpu/ppc/ppc970/Config.lb @@ -11,5 +11,12 @@ uses USE_DCACHE_RAM ## default USE_DCACHE_RAM=0 -initinclude "FAMILY_INIT" cpu/ppc/ppc970/ppc970.inc +initinclude "EXCEPTION_VECTOR_TABLE" cpu/ppc/ppc970/ppc970excp.S +initinclude "PROCESSOR_INIT" cpu/ppc/ppc970/ppc970.inc + +object clock.o +initobject clock.o +initobject ppc970lib.S + +dir /cpu/simple_init diff --git a/src/cpu/ppc/ppc970/clock.c b/src/cpu/ppc/ppc970/clock.c new file mode 100644 index 0000000000..bb600c6d5b --- /dev/null +++ b/src/cpu/ppc/ppc970/clock.c @@ -0,0 +1,27 @@ +#include + +static int PLL_multiplier[] = { + 25, /* 0000 - 2.5x */ + 75, /* 0001 - 7.5x */ + 70, /* 0010 - 7x */ + 10, /* 0011 - bypass */ + 20, /* 0100 - 2x */ + 65, /* 0101 - 6.5x */ + 100, /* 0110 - 10x */ + 45, /* 0111 - 4.5x */ + 30, /* 1000 - 3x */ + 55, /* 1001 - 5.5x */ + 40, /* 1010 - 4x */ + 50, /* 1011 - 5x */ + 80, /* 1100 - 8x */ + 60, /* 1101 - 6x */ + 35, /* 1110 - 3.5x */ + 0, /* 1111 - off */ +}; + +unsigned long +get_timer_freq(void) +{ + unsigned long clock = CONFIG_SYS_CLK_FREQ * 1000000; + return clock * PLL_multiplier[ppc_gethid1() >> 28] / 10; +} diff --git a/src/cpu/ppc/ppc970/ppc970.inc b/src/cpu/ppc/ppc970/ppc970.inc index b9a4013aad..8ee70c78b7 100644 --- a/src/cpu/ppc/ppc970/ppc970.inc +++ b/src/cpu/ppc/ppc970/ppc970.inc @@ -1,365 +1,555 @@ -/*bsp_970fx/bootlib/init_core.s, pibs_970, pibs_970_1.0 1/14/05 14:58:41*/ -/*----------------------------------------------------------------------------+ -| COPYRIGHT I B M CORPORATION 2002, 2004 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -| US Government Users Restricted Rights - Use, duplication or -| disclosure restricted by GSA ADP Schedule Contract with -| IBM Corp. -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| PPC970FX BSP for EPOS -| Author: Maciej P. Tyrlik -| Component: Boot library. -| File: init_core.s -| Purpose: Basic PPC405 core initialization. -| Changes: -| Date: Comment: -| ----- -------- -| 29-Jan-02 Created MPT -| 30-Jan-02 Completed MPT -| 19-Apr-02 Changed some instructions to macros so that new GCC AS worksMPT -| 23-Apr-02 Removed critical interrupt enabling after rfi MPT -| 31-Jul-02 Fixed data cache invalidate code MPT -| 01-Feb-03 Ported to Argan 7XXFX CRB -| 07-Aug-03 Ported to PPC7XXGX CRB -| 12-Sep-03 Removed PVR definitions, now in board include file MCG -| 16-Sep-03 Do not enable HID0[MUM] or L2CR[L2CE] if 7XXGX DD1.0 MCG -| 31-Oct-03 Enable cache for MV64460 integrated SRAM MCG -| 07-Jan-04 Initialize FPRs to avoid errata. MCG -| 10-Feb-04 Port to PPC970FX MPT -+----------------------------------------------------------------------------*/ - -#include - -/*----------------------------------------------------------------------------+ -| Local defines. -+----------------------------------------------------------------------------*/ -#define INITIAL_SLB_VSID_VAL 0x0000000000000C00 -#define INITIAL_SLB_ESID_VAL 0x0000000008000000 -#define INITIAL_SLB_INVA_VAL 0x0000000000000000 - -/*----------------------------------------------------------------------------+ -| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0. -| Data cahability must be turned on. Instruction cahability must be off. -+----------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------+ - | Set time base to 0. - +--------------------------------------------------------------------*/ - addi r4,r0,0x0000 - mtspr SPR_TBU_WRITE,r4 - mtspr SPR_TBL_WRITE,r4 - /*--------------------------------------------------------------------+ - | Set HID1[10] to 0 (instruction cache off) and set HID4[23] to 0 (data - | cache on), set HID4[DC_SET1] and HID4[DC_SET2] to 0. - +--------------------------------------------------------------------*/ - LOAD_64BIT_VAL(r4,HID1_EN_IC) - nor r4,r4,r4 - mfspr r5,SPR_HID1 - isync - and r5,r5,r4 - mtspr SPR_HID1,r5 - mtspr SPR_HID1,r5 - isync - LOAD_64BIT_VAL(r4,HID4_RM_CI|HID4_DC_SET1|HID4_DC_SET2) - nor r4,r4,r4 - mfspr r5,SPR_HID4 - LOAD_64BIT_VAL(r6,HID4_L1DC_FLSH) - isync - and r5,r5,r4 - or r5,r5,r6 - sync - mtspr SPR_HID4,r5 - isync - /*--------------------------------------------------------------------+ - | Clear the flash invalidate L1 data cache bit in HID4. - +--------------------------------------------------------------------*/ - nor r6,r6,r6 - and r5,r5,r6 - sync - mtspr SPR_HID4,r5 - isync - /*--------------------------------------------------------------------+ - | Clear and set up some registers. - +--------------------------------------------------------------------*/ - addi r4,r0,0x0000 - mtxer r4 - /*--------------------------------------------------------------------+ - | Invalidate SLB. First load SLB with known values then perform - | invalidate. Invalidate will clear the D-ERAT and I-ERAT. The SLB - | is 64 entry fully associative. On power on D-ERAT and I-ERAT are all - | set to invalid values. - +--------------------------------------------------------------------*/ - addi r5,r0,SLB_SIZE - mtctr r5 - LOAD_64BIT_VAL(r6,INITIAL_SLB_VSID_VAL) - LOAD_64BIT_VAL(r7,INITIAL_SLB_ESID_VAL) - addis r8,r0,0x1000 -0: slbmte r6,r7 - addi r6,r6,0x1000 - add r7,r7,r8 - addi r7,r7,0x0001 - bdnz 0b - mtctr r5 - LOAD_64BIT_VAL(r6,INITIAL_SLB_INVA_VAL) -1: slbie r6 - add r6,r6,r8 - bdnz 1b - /*--------------------------------------------------------------------+ - | Load SLB. Following is the initial memory map. - | Entry(6) ESID(36) VSID - | 0x0 0x000000000 0x0000000000000 (large page cachable) - | 0x1 0x00000000F 0x000000000000F (small non-cachable, G) - | at 0x00000000 there will be 48MB mapped (SDRAM) - | at 0xF8000000 there will be 16MB mapped (NB) - | at 0xF4000000 there will be 64KB mapped (I/O space) - | at 0xFF000000 there will be 16MB or 1MB mapped (FLASH) - +--------------------------------------------------------------------*/ - addi r6,r0,0x0100 - addis r7,r0,0x0800 - slbmte r6,r7 - addi r6,r0,0x0000 - ori r6,r6,0xF000 - addi r7,r0,0x0001 - oris r7,r7,0xF800 - slbmte r6,r7 - /*--------------------------------------------------------------------+ - | Invalidate all 1024 instruction and data TLBs (4 way) - +--------------------------------------------------------------------*/ - addi r8,r0,0x0100 - mtspr CTR,r8 - addi r8,r0,0x0000 -2: TLBIEL(r8) - addi r8,r8,0x1000 - bdnz 2b - ptesync - /*--------------------------------------------------------------------+ - | Dcbz the page table space. Calculate SDR1 address. Store SDR1 - | address in r30. - +--------------------------------------------------------------------*/ - mfspr r3,SPR_PIR - cmpi cr0,1,r3,0x0000 - bne 3f - addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU0@h - ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU0@l - b 4f -3: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h - ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU1@l -4: addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h - ori r4,r4,INITIAL_PAGE_TABLE_SIZE@l - rlwinm r5,r4,14,14,31 - cntlzw r5,r5 - subfic r5,r5,31 - or r30,r3,r5 - bl .ppcDcbz_area - /*--------------------------------------------------------------------+ - | Setup 0x00000000FFFFFFFF mask in r29. - +--------------------------------------------------------------------*/ - addi r29,r0,0x0001 - rldicl r29,r29,32,31 - addi r29,r29,-1 - /*--------------------------------------------------------------------+ - | Setup 48MB of addresses in DRAM in page table (3 large PTE). The - | parameters to p_ptegg are: r3 = lp, r4 = ea, r5 = sdr1, r6 = vsid. - +--------------------------------------------------------------------*/ - addi r3,r0,0x0001 - addi r4,r0,0x0000 - ori r5,r30,0x0000 - addi r6,r0,0x0000 - bl .p_ptegg - addi r4,r0,0x0001 - stw r4,0x0004(r3) - addi r4,r0,0x0180 - stw r4,0x000C(r3) - /*--------------------------------------------------------------------+ - | Second 16MB is mapped here. - +--------------------------------------------------------------------*/ - addi r3,r0,0x0001 - addis r4,r0,0x0100 - ori r5,r30,0x0000 - addi r6,r0,0x0000 - bl .p_ptegg - addi r4,r0,0x0101 - stw r4,0x0004(r3) - addis r4,r0,0x0100 - ori r4,r4,0x0180 - stw r4,0x000C(r3) - /*--------------------------------------------------------------------+ - | Third 16MB is mapped here. - +--------------------------------------------------------------------*/ - addi r3,r0,0x0001 - addis r4,r0,0x0200 - ori r5,r30,0x0000 - addi r6,r0,0x0000 - bl .p_ptegg - addi r4,r0,0x0201 - stw r4,0x0004(r3) - addis r4,r0,0x0200 - ori r4,r4,0x0180 - stw r4,0x000C(r3) - /*--------------------------------------------------------------------+ - | Setup 64KB of addresses in I/O space (0xF4000000). - +--------------------------------------------------------------------*/ - addi r3,r0,0x0010 - mtctr r3 - addis r31,r0,0xF400 - and r31,r31,r29 -5: addi r3,r0,0x0000 - ori r4,r31,0x0000 - ori r5,r30,0x0000 - addi r6,r0,0x000F - bl .p_ptegg - addi r6,r3,0x0080 -6: lwz r4,0x0004(r3) - cmpli cr0,1,r4,0x0000 - beq 8f - addi r3,r3,0x0010 - cmp cr0,1,r3,r6 - blt 6b -7: b 7b -8: rlwinm r4,r31,16,4,24 - ori r4,r4,0x0001 - stw r4,0x0004(r3) - ori r4,r31,0x01AC - stw r4,0x000C(r3) - addi r31,r31,0x1000 - bdnz 5b - /*--------------------------------------------------------------------+ - | Setup 16MB of addresses in NB register space (0xF8000000). - +--------------------------------------------------------------------*/ - addi r3,r0,0x1000 - mtctr r3 - addis r31,r0,0xF800 - and r31,r31,r29 -9: addi r3,r0,0x0000 - ori r4,r31,0x0000 - ori r5,r30,0x0000 - addi r6,r0,0x000F - bl .p_ptegg - addi r6,r3,0x0080 -10: lwz r4,0x0004(r3) - cmpli cr0,1,r4,0x0000 - beq 12f - addi r3,r3,0x0010 - cmp cr0,1,r3,r6 - blt 10b -11: b 11b -12: rlwinm r4,r31,16,4,24 - ori r4,r4,0x0001 - stw r4,0x0004(r3) - ori r4,r31,0x01AC - stw r4,0x000C(r3) - addi r31,r31,0x1000 - bdnz 9b - /*--------------------------------------------------------------------+ - | Setup 16MB or 1MB of addresses in ROM (at 0xFF000000 or 0xFFF00000). - +--------------------------------------------------------------------*/ - mfspr r3,SPR_HIOR - LOAD_64BIT_VAL(r4,BOOT_BASE_AS) - cmpd cr0,r3,r4 - beq 13f - addi r3,r0,0x0100 - mtctr r3 - addis r31,r0,0xFFF0 - b 14f -13: addi r3,r0,0x1000 - mtctr r3 - addis r31,r0,0xFF00 -14: and r31,r31,r29 -15: addi r3,r0,0x0000 - ori r4,r31,0x0000 - ori r5,r30,0x0000 - addi r6,r0,0x000F - bl .p_ptegg - addi r6,r3,0x0080 -16: lwz r4,0x0004(r3) - cmpli cr0,1,r4,0x0000 - beq 18f - addi r3,r3,0x0010 - cmp cr0,1,r3,r6 - blt 16b -17: b 17b -18: rlwinm r4,r31,16,4,24 - ori r4,r4,0x0001 - stw r4,0x0004(r3) - ori r4,r31,0x01A3 - stw r4,0x000C(r3) - addi r31,r31,0x1000 - bdnz 15b - /*--------------------------------------------------------------------+ - | Synchronize after setting up page table. - +--------------------------------------------------------------------*/ - ptesync - /*--------------------------------------------------------------------+ - | Set the SDR1 register. - +--------------------------------------------------------------------*/ - mtspr SPR_SDR1,r30 - /*--------------------------------------------------------------------+ - | Clear SRR0, SRR1. - +--------------------------------------------------------------------*/ - addi r0,r0,0x0000 - mtspr SPR_SRR0,r0 - mtspr SPR_SRR1,r0 - /*--------------------------------------------------------------------+ - | Setup for subsequent MSR[ME] initialization to enable machine checks - | and translation. - +--------------------------------------------------------------------*/ - mfmsr r3 - ori r3,r3,(MSR_ME|MSR_IS|MSR_DS|MSR_FP) - mtsrr1 r3 - mtmsrd r3,0 - isync - /*--------------------------------------------------------------------+ - | Setup HID registers (HID0, HID1, HID4, HID5). When HIOR is set to - | 0 HID0 external time base bit is inherited from current HID0. When - | HIOR is set to FLASH_BASE_INTEL_AS then HID0 external time base bit - | is set to 1 in order to indicate that the tiembase is driven by - | external source. When HIOR is greater than FLASH_BASE_INTEL_AS then - | HID0 external time base bit is set to 0 in order to indicate that the - | tiembase is driven from internal clock. - +--------------------------------------------------------------------*/ - LOAD_64BIT_VAL(r6,HID0_EXT_TB_EN) - LOAD_64BIT_VAL(r7,FLASH_BASE_INTEL_AS) - mfspr r5,SPR_HIOR - cmpdi cr0,r5,0x0000 - beq 19f - cmpd cr0,r5,r7 - beq 20f - addi r8,r0,0x0000 - b 21f -20: ori r8,r6,0x0000 - b 21f -19: mfspr r5,SPR_HID0 - and r8,r5,r6 -21: LOAD_64BIT_VAL(r4,HID0_PREFEAR) - andc r4,r4,r6 - or r4,r4,r8 - sync - mtspr SPR_HID0,r4 - mfspr r4,SPR_HID0 - mfspr r4,SPR_HID0 - mfspr r4,SPR_HID0 - mfspr r4,SPR_HID0 - mfspr r4,SPR_HID0 - mfspr r4,SPR_HID0 - LOAD_64BIT_VAL(r4,HID1_PREFEAR) - mtspr SPR_HID1,r4 - mtspr SPR_HID1,r4 - isync - LOAD_64BIT_VAL(r4,HID4_PREFEAR) - sync - mtspr SPR_HID4,r4 - isync - sync - LOAD_64BIT_VAL(r4,HID5_PREFEAR) - mtspr SPR_HID5,r4 - isync - /*--------------------------------------------------------------------+ - | Synchronize memory accesses (sync). - +--------------------------------------------------------------------*/ - sync - LOAD_64BIT_VAL(r0,.init_chip) - mfspr r1,SPR_HIOR - or r0,r0,r1 - eieio - mtspr SPR_SRR0,r0 - rfid + +#include + +/******** init_core.s ***************/ +/*----------------------------------------------------------------------------+ +| Local defines. ++----------------------------------------------------------------------------*/ +#define INITIAL_SLB_VSID_VAL 0x0000000000000C00 +#define INITIAL_SLB_ESID_VAL 0x0000000008000000 +#define INITIAL_SLB_INVA_VAL 0x0000000000000000 + +/*----------------------------------------------------------------------------+ +| Init_core. Assumption: hypervisor on, 64-bit on, HID1[10]=0, HID4[23]=0. +| Data cahability must be turned on. Instruction cahability must be off. ++----------------------------------------------------------------------------*/ +function_prolog(init_core) + /*--------------------------------------------------------------------+ + | Set time base to 0. + +--------------------------------------------------------------------*/ + addi r4,r0,0x0000 + mtspr SPR_TBU_WRITE,r4 + mtspr SPR_TBL_WRITE,r4 + /*--------------------------------------------------------------------+ + | Set HID1[10] to 0 (instruction cache off) and set HID4[23] to 0 (data + | cache on), set HID4[DC_SET1] and HID4[DC_SET2] to 0. + +--------------------------------------------------------------------*/ + LOAD_64BIT_VAL(r4,HID1_EN_IC) + nor r4,r4,r4 + mfspr r5,SPR_HID1 + isync + and r5,r5,r4 + mtspr SPR_HID1,r5 + mtspr SPR_HID1,r5 + isync + LOAD_64BIT_VAL(r4,HID4_RM_CI|HID4_DC_SET1|HID4_DC_SET2) + nor r4,r4,r4 + mfspr r5,SPR_HID4 + LOAD_64BIT_VAL(r6,HID4_L1DC_FLSH) + isync + and r5,r5,r4 + or r5,r5,r6 + sync + mtspr SPR_HID4,r5 + isync + /*--------------------------------------------------------------------+ + | Clear the flash invalidate L1 data cache bit in HID4. + +--------------------------------------------------------------------*/ + nor r6,r6,r6 + and r5,r5,r6 + sync + mtspr SPR_HID4,r5 + isync + /*--------------------------------------------------------------------+ + | Clear and set up some registers. + +--------------------------------------------------------------------*/ + addi r4,r0,0x0000 + mtxer r4 + /*--------------------------------------------------------------------+ + | Invalidate SLB. First load SLB with known values then perform + | invalidate. Invalidate will clear the D-ERAT and I-ERAT. The SLB + | is 64 entry fully associative. On power on D-ERAT and I-ERAT are all + | set to invalid values. + +--------------------------------------------------------------------*/ + addi r5,r0,SLB_SIZE + mtctr r5 + LOAD_64BIT_VAL(r6,INITIAL_SLB_VSID_VAL) + LOAD_64BIT_VAL(r7,INITIAL_SLB_ESID_VAL) + addis r8,r0,0x1000 +..slbl: slbmte r6,r7 + addi r6,r6,0x1000 + add r7,r7,r8 + addi r7,r7,0x0001 + bdnz ..slbl + mtctr r5 + LOAD_64BIT_VAL(r6,INITIAL_SLB_INVA_VAL) +..slbi: slbie r6 + add r6,r6,r8 + bdnz ..slbi + /*--------------------------------------------------------------------+ + | Load SLB. Following is the initial memory map. + | Entry(6) ESID(36) VSID + | 0x0 0x000000000 0x0000000000000 (large page cachable) + | 0x1 0x00000000F 0x000000000000F (small non-cachable, G) + | at 0x00000000 there will be 32MB mapped (SDRAM) + | at 0xF8000000 there will be 16MB mapped (NB) + | at 0xF4000000 there will be 64KB mapped (I/O space) + | at 0xFF000000 there will be 16MB or 1MB mapped (FLASH) + +--------------------------------------------------------------------*/ + addi r6,r0,0x0100 + addis r7,r0,0x0800 + slbmte r6,r7 + addi r6,r0,0x0000 + ori r6,r6,0xF000 + addi r7,r0,0x0001 + oris r7,r7,0xF800 + slbmte r6,r7 + /*--------------------------------------------------------------------+ + | Invalidate all 1024 instruction and data TLBs (4 way) + +--------------------------------------------------------------------*/ + addi r8,r0,0x0100 + mtspr ctr,r8 + addi r8,r0,0x0000 +..ivt: TLBIEL(r8) + addi r8,r8,0x1000 + bdnz ..ivt + ptesync + /*--------------------------------------------------------------------+ + | Dcbz the page table space. Calculate SDR1 address. Store SDR1 + | address in r30. + +--------------------------------------------------------------------*/ + mfspr r3,SPR_PIR + cmpi cr0,1,r3,0x0000 + bne ..cpu1_init_core + addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU0@h + ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU0@l + b ..skcpu +..cpu1_init_core: addis r3,r0,INITIAL_PAGE_TABLE_ADDR_CPU1@h + ori r3,r3,INITIAL_PAGE_TABLE_ADDR_CPU1@l +..skcpu:addis r4,r0,INITIAL_PAGE_TABLE_SIZE@h + ori r4,r4,INITIAL_PAGE_TABLE_SIZE@l + rlwinm r5,r4,14,14,31 + cntlzw r5,r5 + subfic r5,r5,31 + or r30,r3,r5 + bl .ppcDcbz_area + /*--------------------------------------------------------------------+ + | Setup 0x00000000FFFFFFFF mask in r29. + +--------------------------------------------------------------------*/ + addi r29,r0,0x0001 + rldicl r29,r29,32,31 + addi r29,r29,-1 + /*--------------------------------------------------------------------+ + | Setup 32MB of addresses in DRAM in page table (2 large PTE). The + | parameters to p_ptegg are: r3 = lp, r4 = ea, r5 = sdr1, r6 = vsid. + +--------------------------------------------------------------------*/ + addi r3,r0,0x0001 + addi r4,r0,0x0000 + ori r5,r30,0x0000 + addi r6,r0,0x0000 + bl .p_ptegg + addi r4,r0,0x0001 + stw r4,0x0004(r3) + addi r4,r0,0x0180 + stw r4,0x000C(r3) + /*--------------------------------------------------------------------+ + | Second 32MB is mapped here. + +--------------------------------------------------------------------*/ + addi r3,r0,0x0001 + addis r4,r0,0x0100 + ori r5,r30,0x0000 + addi r6,r0,0x0000 + bl .p_ptegg + addi r4,r0,0x0101 + stw r4,0x0004(r3) + addis r4,r0,0x0100 + ori r4,r4,0x0180 + stw r4,0x000C(r3) + /*--------------------------------------------------------------------+ + | Setup 64KB of addresses in I/O space (0xF4000000). + +--------------------------------------------------------------------*/ + addi r3,r0,0x0010 + mtctr r3 + addis r31,r0,0xF400 + and r31,r31,r29 +..aF4: addi r3,r0,0x0000 + ori r4,r31,0x0000 + ori r5,r30,0x0000 + addi r6,r0,0x000F + bl .p_ptegg + addi r6,r3,0x0080 +..aF4a: lwz r4,0x0004(r3) + cmpli cr0,1,r4,0x0000 + beq ..aF4s + addi r3,r3,0x0010 + cmp cr0,1,r3,r6 + blt ..aF4a +..aF4h: b ..aF4h +..aF4s: rlwinm r4,r31,16,4,24 + ori r4,r4,0x0001 + stw r4,0x0004(r3) + ori r4,r31,0x01AC + stw r4,0x000C(r3) + addi r31,r31,0x1000 + bdnz ..aF4 + /*--------------------------------------------------------------------+ + | Setup 16MB of addresses in NB register space (0xF8000000). + +--------------------------------------------------------------------*/ + addi r3,r0,0x1000 + mtctr r3 + addis r31,r0,0xF800 + and r31,r31,r29 +..aF8: addi r3,r0,0x0000 + ori r4,r31,0x0000 + ori r5,r30,0x0000 + addi r6,r0,0x000F + bl .p_ptegg + addi r6,r3,0x0080 +..aF8a: lwz r4,0x0004(r3) + cmpli cr0,1,r4,0x0000 + beq ..aF8s + addi r3,r3,0x0010 + cmp cr0,1,r3,r6 + blt ..aF8a +..aF8h: b ..aF8h +..aF8s: rlwinm r4,r31,16,4,24 + ori r4,r4,0x0001 + stw r4,0x0004(r3) + ori r4,r31,0x01AC + stw r4,0x000C(r3) + addi r31,r31,0x1000 + bdnz ..aF8 + /*--------------------------------------------------------------------+ + | Setup 16MB or 1MB of addresses in ROM (at 0xFF000000 or 0xFFF00000). + +--------------------------------------------------------------------*/ + mfspr r3,SPR_HIOR + LOAD_64BIT_VAL(r4,BOOT_BASE_AS) + cmpd cr0,r3,r4 + beq ..big + addi r3,r0,0x0100 + mtctr r3 + addis r31,r0,0xFFF0 + b ..done +..big: addi r3,r0,0x1000 + mtctr r3 + addis r31,r0,0xFF00 +..done: and r31,r31,r29 +..aFF: addi r3,r0,0x0000 + ori r4,r31,0x0000 + ori r5,r30,0x0000 + addi r6,r0,0x000F + bl .p_ptegg + addi r6,r3,0x0080 +..aFFa: lwz r4,0x0004(r3) + cmpli cr0,1,r4,0x0000 + beq ..aFFs + addi r3,r3,0x0010 + cmp cr0,1,r3,r6 + blt ..aFFa +..aFFh: b ..aFFh +..aFFs: rlwinm r4,r31,16,4,24 + ori r4,r4,0x0001 + stw r4,0x0004(r3) + ori r4,r31,0x01A3 + stw r4,0x000C(r3) + addi r31,r31,0x1000 + bdnz ..aFF + /*--------------------------------------------------------------------+ + | Synchronize after setting up page table. + +--------------------------------------------------------------------*/ + ptesync + /*--------------------------------------------------------------------+ + | Set the SDR1 register. + +--------------------------------------------------------------------*/ + mtspr SPR_SDR1,r30 + /*--------------------------------------------------------------------+ + | Clear SRR0, SRR1. + +--------------------------------------------------------------------*/ + addi r0,r0,0x0000 + mtspr SPR_SRR0,r0 + mtspr SPR_SRR1,r0 + /*--------------------------------------------------------------------+ + | Setup for subsequent MSR[ME] initialization to enable machine checks + | and translation. + +--------------------------------------------------------------------*/ + mfmsr r3 + ori r3,r3,(MSR_ME|MSR_IS|MSR_DS|MSR_FP) + mtsrr1 r3 + mtmsrd r3,0 + isync + /*--------------------------------------------------------------------+ + | Setup HID registers (HID0, HID1, HID4, HID5). When HIOR is set to + | 0 HID0 external time base bit is inherited from current HID0. When + | HIOR is set to FLASH_BASE_INTEL_AS then HID0 external time base bit + | is set to 1 in order to indicate that the tiembase is driven by + | external source. When HIOR is greater than FLASH_BASE_INTEL_AS then + | HID0 external time base bit is set to 0 in order to indicate that the + | tiembase is driven from internal clock. + +--------------------------------------------------------------------*/ + LOAD_64BIT_VAL(r6,HID0_EXT_TB_EN) + LOAD_64BIT_VAL(r7,FLASH_BASE_INTEL_AS) + mfspr r5,SPR_HIOR + cmpdi cr0,r5,0x0000 + beq ..hior0 + cmpd cr0,r5,r7 + beq ..hiorl + addi r8,r0,0x0000 + b ..hiors +..hiorl:ori r8,r6,0x0000 + b ..hiors +..hior0:mfspr r5,SPR_HID0 + and r8,r5,r6 +..hiors:LOAD_64BIT_VAL(r4,HID0_PREFEAR) + andc r4,r4,r6 + or r4,r4,r8 + sync + mtspr SPR_HID0,r4 + mfspr r4,SPR_HID0 + mfspr r4,SPR_HID0 + mfspr r4,SPR_HID0 + mfspr r4,SPR_HID0 + mfspr r4,SPR_HID0 + mfspr r4,SPR_HID0 + LOAD_64BIT_VAL(r4,HID1_PREFEAR) + mtspr SPR_HID1,r4 + mtspr SPR_HID1,r4 + isync + LOAD_64BIT_VAL(r4,HID4_PREFEAR) + sync + mtspr SPR_HID4,r4 + isync + sync + LOAD_64BIT_VAL(r4,HID5_PREFEAR) + mtspr SPR_HID5,r4 + isync + /*--------------------------------------------------------------------+ + | Synchronize memory accesses (sync). + +--------------------------------------------------------------------*/ + sync + LOAD_64BIT_VAL(r0,.init_chip) + mfspr r1,SPR_HIOR + or r0,r0,r1 + eieio + mtspr SPR_SRR0,r0 + rfid + function_epilog(init_core) + + +/******** init_chip.s ***************/ +/*----------------------------------------------------------------------------+ +| Local defines. ++----------------------------------------------------------------------------*/ +#define CPU1_DELAY 0x00010000 + +/*----------------------------------------------------------------------------+ +| Init_chip. ++----------------------------------------------------------------------------*/ + function_prolog(init_chip) + /*--------------------------------------------------------------------+ + | Skip if CPU1. + +--------------------------------------------------------------------*/ + mfspr r3,SPR_PIR + cmpi cr0,1,r3,0x0000 + bne ..cpu1 + /*--------------------------------------------------------------------+ + | Initialize the stack in the data cache for the "C" code that gets + | called. + +--------------------------------------------------------------------*/ + addis r3,r0,BOOT_STACK_ADDR@h + ori r3,r3,BOOT_STACK_ADDR@l + addis r4,r0,BOOT_STACK_SIZE@h + ori r4,r4,BOOT_STACK_SIZE@l + add r1,r3,r4 + bl .ppcDcbz_area + addi r1,r1,-stack_frame_min + addi r5,r0,0x0000 + std r5,stack_frame_bc(r1) + /*--------------------------------------------------------------------+ + | Load TOC. Can't use ld since the TOC value might not be aligned on + | double word boundary. + +--------------------------------------------------------------------*/ + bl ..ot_init_chip + .quad .TOC.@tocbase +..ot_init_chip: mflr r3 + lwz r2,0x0000(r3) + lwz r3,0x0004(r3) + rldicr r2,r2,32,31 + or r2,r2,r3 + mfspr r3,SPR_HIOR + or r2,r2,r3 + /*--------------------------------------------------------------------+ + | Code for chip initialization code goes here. Subtractive decoding + | allows access to specified registers. + +--------------------------------------------------------------------*/ + bl .super_io_setup + /*--------------------------------------------------------------------+ + | Setup default serial port using default baud rate. + +--------------------------------------------------------------------*/ +// bl .sinit_default_no_global + /*--------------------------------------------------------------------+ + | Enable SDRAM only if running from FLASH. + +--------------------------------------------------------------------*/ + mflr r3 + LOAD_64BIT_VAL(r4,BOOT_BASE_AS) + cmpld cr0,r3,r4 + blt ..skip + bl memory_init + /*--------------------------------------------------------------------+ + | Check the memory where PIBS data section will be placed. + +--------------------------------------------------------------------*/ +..skip: bl ..skip_data + .string "\nMemory check failed at 0x%x, expected 0x%x, actual 0x%x" + .align 2 +..skip_data: + addis r3,r0,MEM_CHK_START_ADDR@h + ori r3,r3,MEM_CHK_START_ADDR@l + addis r4,r0,MEM_CHK_SIZE@h + ori r4,r4,MEM_CHK_SIZE@l + mflr r5 +// bl mem_check + /*--------------------------------------------------------------------+ + | Initialize RAM area that holds boot information for CPU1. + +--------------------------------------------------------------------*/ + LOAD_64BIT_VAL(r31,CPU1_DATA_STRUCT_ADDR) + addi r3,r0,0x0000 + std r3,CPU1_DATA_STRUCT_VALID_OFF(r31) + /*--------------------------------------------------------------------+ + | DCBZ area stack is left in the cache since there is no way to + | invalidate data cache. This area will be written to memory at some + | point. Main memory should be functional at this point. + +--------------------------------------------------------------------*/ + b .init_data + /*--------------------------------------------------------------------+ + | CPU1 will spin waiting for the CPU0 to initialize the system. CPU1 + | then will check if the image for CPU1 has been loaded. If the image + | for CPU1 has been loaded CPU1 will jump to that image. If the image + | for CPU1 has not been loaded CPU1 will spin waiting for the image to + | be loaded. + +--------------------------------------------------------------------*/ +..cpu1: LOAD_64BIT_VAL(r31,NB_HW_INIT_STATE_ASM) + lwz r30,0x0000(r31) + cmpi cr0,1,r30,0x0000 + beq ..cpu1 + /*--------------------------------------------------------------------+ + | Jump to SDRAM (cachable storage) and wait there. + +--------------------------------------------------------------------*/ + sync + ba ..loada + /*--------------------------------------------------------------------+ + | Wait for image valid indicator. + +--------------------------------------------------------------------*/ +..loada:LOAD_64BIT_VAL(r31,CPU1_DATA_STRUCT_ADDR) + ld r3,CPU1_DATA_STRUCT_VALID_OFF(r31) + cmpi cr0,1,r3,0x0000 + beq ..spin2 + ld r3,CPU1_DATA_STRUCT_SRR0_OFF(r31) + mtspr SPR_SRR0,r3 + ld r4,CPU1_DATA_STRUCT_SRR1_OFF(r31) + mtspr SPR_SRR1,r4 + ld r3,CPU1_DATA_STRUCT_R3_OFF(r31) + isync + rfid +..spin2:mfspr r29,tblr + LOAD_64BIT_VAL(r31,CPU1_DELAY) +..spin3:mfspr r30,tblr + subf r30,r29,r30 + cmp cr0,1,r30,r31 + blt ..spin3 + b ..loada + function_epilog(init_chip) + + +/******** init_data.s ***************/ +/*----------------------------------------------------------------------------+ +| Init_data. ++----------------------------------------------------------------------------*/ + function_prolog(init_data) + /*--------------------------------------------------------------------+ + | Check if we are running from FLASH. If running from FLASH copy 1M + | of FLASH to SDRAM. + +--------------------------------------------------------------------*/ + bl ..next +..next: mflr r3 + LOAD_64BIT_VAL(r4,BOOT_BASE_AS) + cmpld cr0,r3,r4 + blt ..sk_c + /*--------------------------------------------------------------------+ + | Perform the copy operation. This copies data starting from SPR_HIOR + | for number of bytes queal to __edata - __stext. + +--------------------------------------------------------------------*/ + LOAD_64BIT_VAL(r6,__stext) + addi r3,r6,-8 + mfspr r4,SPR_HIOR + addi r4,r4,-8 + LOAD_64BIT_VAL(r5,__edata); + sub r5,r5,r6 + rlwinm r5,r5,29,3,31 + addi r5,r5,0x0001 + mtctr r5 +..again1:ldu r6,0x0008(r4) + stdu r6,0x0008(r3) + bdnz ..again1 + /*--------------------------------------------------------------------+ + | Get the size of BSS into r6. + +--------------------------------------------------------------------*/ +..sk_c: LOAD_64BIT_VAL(r4,__sbss) + LOAD_64BIT_VAL(r5,__ebss) + sub r6,r5,r4 + /*--------------------------------------------------------------------+ + | Clear BSS. + +--------------------------------------------------------------------*/ + addi r8,r4,-1 + mtspr ctr,r6 + addi r9,r0,0x0000 +..bag: stbu r9,0x0001(r8) + bdnz ..bag + /*--------------------------------------------------------------------+ + | Synchronize. + +--------------------------------------------------------------------*/ + sync + ba .init_cenv + function_epilog(init_data) + + +/******** init_cenv.s ***************/ +/*----------------------------------------------------------------------------+ +| TOC entry for __initial_stack. ++----------------------------------------------------------------------------*/ +TOC_ENTRY(.LC0,__initial_stack) + +/*----------------------------------------------------------------------------+ +| Initial stack. ++----------------------------------------------------------------------------*/ + data_prolog(__initial_stack) + .space MY_MAIN_STACK_SIZE + data_epilog(__initial_stack) + +/*----------------------------------------------------------------------------+ +| Init_cenv. ++----------------------------------------------------------------------------*/ + function_prolog(init_cenv) + /*--------------------------------------------------------------------+ + | Load TOC. Can't use ld since the TOC value might not be aligned on + | double word boundary. R2 is loaded for the first time here when + | loaded by PIBS (second time when originally running from FLASH). + +--------------------------------------------------------------------*/ + bl ..ot + .quad .TOC.@tocbase +..ot: mflr r3 + lwz r2,0x0000(r3) + lwz r3,0x0004(r3) + rldicr r2,r2,32,31 + or r2,r2,r3 + /*--------------------------------------------------------------------+ + | Get the address and size of the stack. + +--------------------------------------------------------------------*/ + GETSYMADDR(r3,__initial_stack,.LC0) + addis r4,r0,MY_MAIN_STACK_SIZE@h + ori r4,r4,MY_MAIN_STACK_SIZE@l + /*--------------------------------------------------------------------+ + | Setup the stack, stack bust be quadword (128-bit) aligned. + +--------------------------------------------------------------------*/ + add r1,r3,r4 + addi r1,r1,-stack_frame_min + rldicr r1,r1,0,59 + addi r5,r0,0x0000 + std r5,stack_frame_bc(r1) + std r5,stack_frame_lr(r1) + /*--------------------------------------------------------------------+ + | Call the "C" function. + +--------------------------------------------------------------------*/ +// b .my_main + b .ppc_main +..spin: b ..spin + function_epilog(init_cenv) + diff --git a/src/cpu/ppc/ppc970/ppc970excp.S b/src/cpu/ppc/ppc970/ppc970excp.S new file mode 100755 index 0000000000..f14eaa22c2 --- /dev/null +++ b/src/cpu/ppc/ppc970/ppc970excp.S @@ -0,0 +1,11 @@ + +#include + +/*----------------------------------------------------------------------------+ +| Init_excp. The external interrupt vector should never be called before +| io_init() is called so it can be removed from this file. ++----------------------------------------------------------------------------*/ + function_prolog(init_excp) + .space 0x100 + b .init_core /* 0100 */ + function_epilog(init_excp) diff --git a/src/cpu/ppc/ppc970/ppc970lib.S b/src/cpu/ppc/ppc970/ppc970lib.S new file mode 100755 index 0000000000..0d20e24a39 --- /dev/null +++ b/src/cpu/ppc/ppc970/ppc970lib.S @@ -0,0 +1,5027 @@ + +#include "ppc970.h" + +/*----------------------------------------------------------------------------+ +| PpcMflr ++----------------------------------------------------------------------------*/ + function_prolog(ppcMflr) + mflr r3 + blr + function_epilog(ppcMflr) + +/*----------------------------------------------------------------------------+ +| Inbyte ++----------------------------------------------------------------------------*/ + function_prolog(inbyte) + lbz r3,0x0000(r3) + sync + blr + function_epilog(inbyte) + +/*----------------------------------------------------------------------------+ +| Outbyte ++----------------------------------------------------------------------------*/ + function_prolog(outbyte) + stb r4,0x0000(r3) + sync + blr + function_epilog(outbyte) + +/*----------------------------------------------------------------------------+ +| Inhalf ++----------------------------------------------------------------------------*/ + function_prolog(inhalf) + lhz r3,0x0000(r3) + sync + blr + function_epilog(inhalf) + +/*----------------------------------------------------------------------------+ +| Outhalf ++----------------------------------------------------------------------------*/ + function_prolog(outhalf) + sth r4,0x0000(r3) + sync + blr + function_epilog(outhalf) + +/*----------------------------------------------------------------------------+ +| Inhalf_brx (Load halfword byte-reverse indexed) ++----------------------------------------------------------------------------*/ + function_prolog(inhalf_brx) + lhbrx r3,r0,r3 + sync + blr + function_epilog(inhalf_brx) + +/*----------------------------------------------------------------------------+ +| Outhalf_brx (Store halfword byte-reverse indexed) ++----------------------------------------------------------------------------*/ + function_prolog(outhalf_brx) + sthbrx r4,r0,r3 + sync + blr + function_epilog(outhalf_brx) + +/*----------------------------------------------------------------------------+ +| Inword ++----------------------------------------------------------------------------*/ + function_prolog(inword) + ld r3,0x0000(r3) + sync + blr + function_epilog(inword) + +/*----------------------------------------------------------------------------+ +| Outword ++----------------------------------------------------------------------------*/ + function_prolog(outword) + std r4,0x0000(r3) + sync + blr + function_epilog(outword) + +/*----------------------------------------------------------------------------+ +| Inint ++----------------------------------------------------------------------------*/ + function_prolog(inint) + lwz r3,0x0000(r3) + sync + blr + function_epilog(inint) + +/*----------------------------------------------------------------------------+ +| Outint ++----------------------------------------------------------------------------*/ + function_prolog(outint) + stw r4,0x0000(r3) + sync + blr + function_epilog(outint) + +/*----------------------------------------------------------------------------+ +| Inint_brx (Load word byte-reverse indexed) ++----------------------------------------------------------------------------*/ + function_prolog(inint_brx) + lwbrx r3,r0,r3 + sync + blr + function_epilog(inint_brx) + +/*----------------------------------------------------------------------------+ +| Outint_brx (Store word byte-reverse indexed) ++----------------------------------------------------------------------------*/ + function_prolog(outint_brx) + stwbrx r4,r0,r3 + sync + blr + function_epilog(outint_brx) + +/*----------------------------------------------------------------------------+ +| PpcDflush. Assume addresses 0-2MB are cachable. Do a series of loads to +| fill the L2 using a memory range twice as large as the L2 in case a line +| between 0-2MB is dirty in the L2 to start. ++----------------------------------------------------------------------------*/ + function_prolog(ppcDflush) + mfmsr r9 + rlwinm r8,r9,0,17,15 + mtmsrd r8,1 + isync + /*--------------------------------------------------------------------+ + | Back to the initial start address. + +--------------------------------------------------------------------*/ + addi r3,r0,0x0000 + addis r4,r0,0x0000 + /*--------------------------------------------------------------------+ + | 2x number of blocks in 512KB L2 cache. + +--------------------------------------------------------------------*/ + ori r4,r4,0x2000 + mtctr r4 +..fl: lwz r6,0x0(r3) + addi r3,r3,128 + bdnz ..fl + sync + /*--------------------------------------------------------------------+ + | Now flush the last lines. + +--------------------------------------------------------------------*/ + addis r3,r0,0x0008 + ori r4,r4,0x1000 + mtctr r4 +..fl1: dcbf r0,r3 + addi r3,r3,123 + bdnz ..fl1 + /*--------------------------------------------------------------------+ + | No dirty lines should exist in the L2 at this point. + +--------------------------------------------------------------------*/ + mtmsrd r9,1 + isync + blr + function_epilog(ppcDflush) + +/*----------------------------------------------------------------------------+ +| PpcDcbz_area (dcbz: data cache block set to zero). Although the cache line +| in L2 is 128 bytes the dcbz instruction will only zero 32 bytes when HID5 +| bit 56 is set to 0. This function will work with HID5 bit 56 set to 0 or 1. ++----------------------------------------------------------------------------*/ + function_prolog(ppcDcbz_area) + rlwinm. r5,r4,0,27,31 + rlwinm r5,r4,27,5,31 + beq ..d_ran + addi r5,r5,0x0001 +..d_ran:mtctr r5 +..d_ag: dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag + blr + function_epilog(ppcDcbz_area) + +/*----------------------------------------------------------------------------+ +| PpcTlbsync (tlbsync: TLB Synchronize) ++----------------------------------------------------------------------------*/ + function_prolog(ppcTlbsync) + tlbsync + blr + function_epilog(ppcTlbsync) + +/*----------------------------------------------------------------------------+ +| PpcTlbie (tlbie: TLB Invalidate Entry) ++----------------------------------------------------------------------------*/ + function_prolog(ppcTlbie) + cmpi cr0,1,r4,0x0000 + bne ..tlp + tlbie r3,0 + blr +..tlp: tlbie r3,1 + blr + function_epilog(ppcTlbie) + +/*----------------------------------------------------------------------------+ +| PpcAbend ++----------------------------------------------------------------------------*/ + function_prolog(ppcAbend) + .long 0x00000000 + function_epilog(ppcAbend) + +/*----------------------------------------------------------------------------+ +| PpcAndMsr ++----------------------------------------------------------------------------*/ + function_prolog(ppcAndMsr) + mfmsr r6 + and r7,r6,r3 + mtmsrd r7,0 + isync + ori r3,r6,0x000 + blr + function_epilog(ppcAndMsr) + +/*----------------------------------------------------------------------------+ +| PpcCntlzw (cntlzw: count leading zeros word) ++----------------------------------------------------------------------------*/ + function_prolog(ppcCntlzw) + cntlzw r3,r3 + blr + function_epilog(ppcCntlzw) + +/*----------------------------------------------------------------------------+ +| PpcCntlzd (cntlzd: count leading zeros double word) ++----------------------------------------------------------------------------*/ + function_prolog(ppcCntlzd) + cntlzd r3,r3 + blr + function_epilog(ppcCntlzd) + +/*----------------------------------------------------------------------------+ +| PpcDcbf (dcbf: data cache block flush) ++----------------------------------------------------------------------------*/ + function_prolog(ppcDcbf) + dcbf r0,r3 + blr + function_epilog(ppcDcbf) + +/*----------------------------------------------------------------------------+ +| PpcDcbst (dcbst: data cache block touch for store) ++----------------------------------------------------------------------------*/ + function_prolog(ppcDcbst) + dcbst r0,r3 + blr + function_epilog(ppcDcbst) + +/*----------------------------------------------------------------------------+ +| PpcDcbz (dcbz: data cache block set to zero) ++----------------------------------------------------------------------------*/ + function_prolog(ppcDcbz) + dcbz r0,r3 + blr + function_epilog(ppcDcbz) + +/*----------------------------------------------------------------------------+ +| PpcHalt (3 nop instructions + branch) ++----------------------------------------------------------------------------*/ + function_prolog(ppcHalt) + ori r0,r0,0x0000 + b .ppcHalt + function_epilog(ppcHalt) + +/*----------------------------------------------------------------------------+ +| PpcIcbi (icbi: instruction cache block invalidate) ++----------------------------------------------------------------------------*/ + function_prolog(ppcIcbi) + icbi r0,r3 + blr + function_epilog(ppcIcbi) + +/*----------------------------------------------------------------------------+ +| PpcIsync (isync: instruction synchronize) ++----------------------------------------------------------------------------*/ + function_prolog(ppcIsync) + isync + blr + function_epilog(ppcIsync) + +/*----------------------------------------------------------------------------+ +| PpcMfgpr1 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMfgpr1) + addi r3,r1,0x0000 + blr + function_epilog(ppcMfgpr1) + +/*----------------------------------------------------------------------------+ +| PpcMfgpr2 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMfgpr2) + addi r3,r2,0x0000 + blr + function_epilog(ppcMfgpr2) + +/*----------------------------------------------------------------------------+ +| PpcMtmsr ++----------------------------------------------------------------------------*/ + function_prolog(ppcMtmsr) + mtmsrd r3,0 + isync + blr + function_epilog(ppcMtmsr) + +/*----------------------------------------------------------------------------+ +| PpcMfmsr ++----------------------------------------------------------------------------*/ + function_prolog(ppcMfmsr) + mfmsr r3 + blr + function_epilog(ppcMfmsr) + +/*----------------------------------------------------------------------------+ +| PpcOrMsr ++----------------------------------------------------------------------------*/ + function_prolog(ppcOrMsr) + mfmsr r6 + or r7,r6,r3 + mtmsrd r7,0 + isync + ori r3,r6,0x000 + blr + function_epilog(ppcOrMsr) + +/*----------------------------------------------------------------------------+ +| PpcSync ++----------------------------------------------------------------------------*/ + function_prolog(ppcSync) + sync + blr + function_epilog(ppcSync) + +/*----------------------------------------------------------------------------+ +| PpcEieio ++----------------------------------------------------------------------------*/ + function_prolog(ppcEieio) + eieio + blr + function_epilog(ppcEieio) + +/*----------------------------------------------------------------------------+ +| PpcMthid0 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMthid0) + sync + mtspr SPR_HID0,r3 + mfspr r3,SPR_HID0 + mfspr r3,SPR_HID0 + mfspr r3,SPR_HID0 + mfspr r3,SPR_HID0 + mfspr r3,SPR_HID0 + mfspr r3,SPR_HID0 + blr + function_epilog(ppcMthid0) + +/*----------------------------------------------------------------------------+ +| PpcMthid1 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMthid1) + mtspr SPR_HID1,r3 + mtspr SPR_HID1,r3 + isync + blr + function_epilog(ppcMthid1) + +/*----------------------------------------------------------------------------+ +| PpcMthid4 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMthid4) + sync + mtspr SPR_HID4,r3 + isync + blr + function_epilog(ppcMthid4) + +/*----------------------------------------------------------------------------+ +| PpcMthid5 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMthid5) + mtspr SPR_HID5,r3 + blr + function_epilog(ppcMthid5) + +/*----------------------------------------------------------------------------+ +| PpcMftb ++----------------------------------------------------------------------------*/ + function_prolog(ppcMftb) + mfspr r6,tblr + std r6,0x0000(r3) + blr + function_epilog(ppcMftb) + +/*----------------------------------------------------------------------------+ +| PpcMttb ++----------------------------------------------------------------------------*/ + function_prolog(ppcMttb) + mfmsr r7 + lwz r6,0x0000(r3) + rlwinm r8,r7,0,17,15 + mtmsrd r8,1 + ori r5,r6,0x0000 + sradi r6,r6,32 + addi r4,r0,0x0000 + rldicl r6,r6,0,32 + mtspr SPR_TBL_WRITE,r4 + mtspr SPR_TBU_WRITE,r6 + mtspr SPR_TBL_WRITE,r5 + mtmsrd r7,1 + blr + function_epilog(ppcMttb) + +/*----------------------------------------------------------------------------+ +| PpcMtspr_any ++----------------------------------------------------------------------------*/ + function_prolog(ppcMtspr_any) + rlwinm r3,r3,3,19,29 + addi r3,r3,0x0010 + mflr r6 + bl ..sp_get_lr +..sp_get_lr: + mflr r5 + add r5,r5,r3 + mtlr r5 + blr + mtspr 0x000,r4 + b ..ppcMtspr_any_end + mtspr 0x001,r4 + b ..ppcMtspr_any_end + mtspr 0x002,r4 + b ..ppcMtspr_any_end + mtspr 0x003,r4 + b ..ppcMtspr_any_end + mtspr 0x004,r4 + b ..ppcMtspr_any_end + mtspr 0x005,r4 + b ..ppcMtspr_any_end + mtspr 0x006,r4 + b ..ppcMtspr_any_end + mtspr 0x007,r4 + b ..ppcMtspr_any_end + mtspr 0x008,r4 + b ..ppcMtspr_any_end + mtspr 0x009,r4 + b ..ppcMtspr_any_end + mtspr 0x00a,r4 + b ..ppcMtspr_any_end + mtspr 0x00b,r4 + b ..ppcMtspr_any_end + mtspr 0x00c,r4 + b ..ppcMtspr_any_end + mtspr 0x00d,r4 + b ..ppcMtspr_any_end + mtspr 0x00e,r4 + b ..ppcMtspr_any_end + mtspr 0x00f,r4 + b ..ppcMtspr_any_end + mtspr 0x010,r4 + b ..ppcMtspr_any_end + mtspr 0x011,r4 + b ..ppcMtspr_any_end + mtspr 0x012,r4 + b ..ppcMtspr_any_end + mtspr 0x013,r4 + b ..ppcMtspr_any_end + mtspr 0x014,r4 + b ..ppcMtspr_any_end + mtspr 0x015,r4 + b ..ppcMtspr_any_end + mtspr 0x016,r4 + b ..ppcMtspr_any_end + mtspr 0x017,r4 + b ..ppcMtspr_any_end + mtspr 0x018,r4 + b ..ppcMtspr_any_end + mtspr 0x019,r4 + b ..ppcMtspr_any_end + mtspr 0x01a,r4 + b ..ppcMtspr_any_end + mtspr 0x01b,r4 + b ..ppcMtspr_any_end + mtspr 0x01c,r4 + b ..ppcMtspr_any_end + mtspr 0x01d,r4 + b ..ppcMtspr_any_end + mtspr 0x01e,r4 + b ..ppcMtspr_any_end + mtspr 0x01f,r4 + b ..ppcMtspr_any_end + mtspr 0x020,r4 + b ..ppcMtspr_any_end + mtspr 0x021,r4 + b ..ppcMtspr_any_end + mtspr 0x022,r4 + b ..ppcMtspr_any_end + mtspr 0x023,r4 + b ..ppcMtspr_any_end + mtspr 0x024,r4 + b ..ppcMtspr_any_end + mtspr 0x025,r4 + b ..ppcMtspr_any_end + mtspr 0x026,r4 + b ..ppcMtspr_any_end + mtspr 0x027,r4 + b ..ppcMtspr_any_end + mtspr 0x028,r4 + b ..ppcMtspr_any_end + mtspr 0x029,r4 + b ..ppcMtspr_any_end + mtspr 0x02a,r4 + b ..ppcMtspr_any_end + mtspr 0x02b,r4 + b ..ppcMtspr_any_end + mtspr 0x02c,r4 + b ..ppcMtspr_any_end + mtspr 0x02d,r4 + b ..ppcMtspr_any_end + mtspr 0x02e,r4 + b ..ppcMtspr_any_end + mtspr 0x02f,r4 + b ..ppcMtspr_any_end + mtspr 0x030,r4 + b ..ppcMtspr_any_end + mtspr 0x031,r4 + b ..ppcMtspr_any_end + mtspr 0x032,r4 + b ..ppcMtspr_any_end + mtspr 0x033,r4 + b ..ppcMtspr_any_end + mtspr 0x034,r4 + b ..ppcMtspr_any_end + mtspr 0x035,r4 + b ..ppcMtspr_any_end + mtspr 0x036,r4 + b ..ppcMtspr_any_end + mtspr 0x037,r4 + b ..ppcMtspr_any_end + mtspr 0x038,r4 + b ..ppcMtspr_any_end + mtspr 0x039,r4 + b ..ppcMtspr_any_end + mtspr 0x03a,r4 + b ..ppcMtspr_any_end + mtspr 0x03b,r4 + b ..ppcMtspr_any_end + mtspr 0x03c,r4 + b ..ppcMtspr_any_end + mtspr 0x03d,r4 + b ..ppcMtspr_any_end + mtspr 0x03e,r4 + b ..ppcMtspr_any_end + mtspr 0x03f,r4 + b ..ppcMtspr_any_end + mtspr 0x040,r4 + b ..ppcMtspr_any_end + mtspr 0x041,r4 + b ..ppcMtspr_any_end + mtspr 0x042,r4 + b ..ppcMtspr_any_end + mtspr 0x043,r4 + b ..ppcMtspr_any_end + mtspr 0x044,r4 + b ..ppcMtspr_any_end + mtspr 0x045,r4 + b ..ppcMtspr_any_end + mtspr 0x046,r4 + b ..ppcMtspr_any_end + mtspr 0x047,r4 + b ..ppcMtspr_any_end + mtspr 0x048,r4 + b ..ppcMtspr_any_end + mtspr 0x049,r4 + b ..ppcMtspr_any_end + mtspr 0x04a,r4 + b ..ppcMtspr_any_end + mtspr 0x04b,r4 + b ..ppcMtspr_any_end + mtspr 0x04c,r4 + b ..ppcMtspr_any_end + mtspr 0x04d,r4 + b ..ppcMtspr_any_end + mtspr 0x04e,r4 + b ..ppcMtspr_any_end + mtspr 0x04f,r4 + b ..ppcMtspr_any_end + mtspr 0x050,r4 + b ..ppcMtspr_any_end + mtspr 0x051,r4 + b ..ppcMtspr_any_end + mtspr 0x052,r4 + b ..ppcMtspr_any_end + mtspr 0x053,r4 + b ..ppcMtspr_any_end + mtspr 0x054,r4 + b ..ppcMtspr_any_end + mtspr 0x055,r4 + b ..ppcMtspr_any_end + mtspr 0x056,r4 + b ..ppcMtspr_any_end + mtspr 0x057,r4 + b ..ppcMtspr_any_end + mtspr 0x058,r4 + b ..ppcMtspr_any_end + mtspr 0x059,r4 + b ..ppcMtspr_any_end + mtspr 0x05a,r4 + b ..ppcMtspr_any_end + mtspr 0x05b,r4 + b ..ppcMtspr_any_end + mtspr 0x05c,r4 + b ..ppcMtspr_any_end + mtspr 0x05d,r4 + b ..ppcMtspr_any_end + mtspr 0x05e,r4 + b ..ppcMtspr_any_end + mtspr 0x05f,r4 + b ..ppcMtspr_any_end + mtspr 0x060,r4 + b ..ppcMtspr_any_end + mtspr 0x061,r4 + b ..ppcMtspr_any_end + mtspr 0x062,r4 + b ..ppcMtspr_any_end + mtspr 0x063,r4 + b ..ppcMtspr_any_end + mtspr 0x064,r4 + b ..ppcMtspr_any_end + mtspr 0x065,r4 + b ..ppcMtspr_any_end + mtspr 0x066,r4 + b ..ppcMtspr_any_end + mtspr 0x067,r4 + b ..ppcMtspr_any_end + mtspr 0x068,r4 + b ..ppcMtspr_any_end + mtspr 0x069,r4 + b ..ppcMtspr_any_end + mtspr 0x06a,r4 + b ..ppcMtspr_any_end + mtspr 0x06b,r4 + b ..ppcMtspr_any_end + mtspr 0x06c,r4 + b ..ppcMtspr_any_end + mtspr 0x06d,r4 + b ..ppcMtspr_any_end + mtspr 0x06e,r4 + b ..ppcMtspr_any_end + mtspr 0x06f,r4 + b ..ppcMtspr_any_end + mtspr 0x070,r4 + b ..ppcMtspr_any_end + mtspr 0x071,r4 + b ..ppcMtspr_any_end + mtspr 0x072,r4 + b ..ppcMtspr_any_end + mtspr 0x073,r4 + b ..ppcMtspr_any_end + mtspr 0x074,r4 + b ..ppcMtspr_any_end + mtspr 0x075,r4 + b ..ppcMtspr_any_end + mtspr 0x076,r4 + b ..ppcMtspr_any_end + mtspr 0x077,r4 + b ..ppcMtspr_any_end + mtspr 0x078,r4 + b ..ppcMtspr_any_end + mtspr 0x079,r4 + b ..ppcMtspr_any_end + mtspr 0x07a,r4 + b ..ppcMtspr_any_end + mtspr 0x07b,r4 + b ..ppcMtspr_any_end + mtspr 0x07c,r4 + b ..ppcMtspr_any_end + mtspr 0x07d,r4 + b ..ppcMtspr_any_end + mtspr 0x07e,r4 + b ..ppcMtspr_any_end + mtspr 0x07f,r4 + b ..ppcMtspr_any_end + mtspr 0x080,r4 + b ..ppcMtspr_any_end + mtspr 0x081,r4 + b ..ppcMtspr_any_end + mtspr 0x082,r4 + b ..ppcMtspr_any_end + mtspr 0x083,r4 + b ..ppcMtspr_any_end + mtspr 0x084,r4 + b ..ppcMtspr_any_end + mtspr 0x085,r4 + b ..ppcMtspr_any_end + mtspr 0x086,r4 + b ..ppcMtspr_any_end + mtspr 0x087,r4 + b ..ppcMtspr_any_end + mtspr 0x088,r4 + b ..ppcMtspr_any_end + mtspr 0x089,r4 + b ..ppcMtspr_any_end + mtspr 0x08a,r4 + b ..ppcMtspr_any_end + mtspr 0x08b,r4 + b ..ppcMtspr_any_end + mtspr 0x08c,r4 + b ..ppcMtspr_any_end + mtspr 0x08d,r4 + b ..ppcMtspr_any_end + mtspr 0x08e,r4 + b ..ppcMtspr_any_end + mtspr 0x08f,r4 + b ..ppcMtspr_any_end + mtspr 0x090,r4 + b ..ppcMtspr_any_end + mtspr 0x091,r4 + b ..ppcMtspr_any_end + mtspr 0x092,r4 + b ..ppcMtspr_any_end + mtspr 0x093,r4 + b ..ppcMtspr_any_end + mtspr 0x094,r4 + b ..ppcMtspr_any_end + mtspr 0x095,r4 + b ..ppcMtspr_any_end + mtspr 0x096,r4 + b ..ppcMtspr_any_end + mtspr 0x097,r4 + b ..ppcMtspr_any_end + mtspr 0x098,r4 + b ..ppcMtspr_any_end + mtspr 0x099,r4 + b ..ppcMtspr_any_end + mtspr 0x09a,r4 + b ..ppcMtspr_any_end + mtspr 0x09b,r4 + b ..ppcMtspr_any_end + mtspr 0x09c,r4 + b ..ppcMtspr_any_end + mtspr 0x09d,r4 + b ..ppcMtspr_any_end + mtspr 0x09e,r4 + b ..ppcMtspr_any_end + mtspr 0x09f,r4 + b ..ppcMtspr_any_end + mtspr 0x0a0,r4 + b ..ppcMtspr_any_end + mtspr 0x0a1,r4 + b ..ppcMtspr_any_end + mtspr 0x0a2,r4 + b ..ppcMtspr_any_end + mtspr 0x0a3,r4 + b ..ppcMtspr_any_end + mtspr 0x0a4,r4 + b ..ppcMtspr_any_end + mtspr 0x0a5,r4 + b ..ppcMtspr_any_end + mtspr 0x0a6,r4 + b ..ppcMtspr_any_end + mtspr 0x0a7,r4 + b ..ppcMtspr_any_end + mtspr 0x0a8,r4 + b ..ppcMtspr_any_end + mtspr 0x0a9,r4 + b ..ppcMtspr_any_end + mtspr 0x0aa,r4 + b ..ppcMtspr_any_end + mtspr 0x0ab,r4 + b ..ppcMtspr_any_end + mtspr 0x0ac,r4 + b ..ppcMtspr_any_end + mtspr 0x0ad,r4 + b ..ppcMtspr_any_end + mtspr 0x0ae,r4 + b ..ppcMtspr_any_end + mtspr 0x0af,r4 + b ..ppcMtspr_any_end + mtspr 0x0b0,r4 + b ..ppcMtspr_any_end + mtspr 0x0b1,r4 + b ..ppcMtspr_any_end + mtspr 0x0b2,r4 + b ..ppcMtspr_any_end + mtspr 0x0b3,r4 + b ..ppcMtspr_any_end + mtspr 0x0b4,r4 + b ..ppcMtspr_any_end + mtspr 0x0b5,r4 + b ..ppcMtspr_any_end + mtspr 0x0b6,r4 + b ..ppcMtspr_any_end + mtspr 0x0b7,r4 + b ..ppcMtspr_any_end + mtspr 0x0b8,r4 + b ..ppcMtspr_any_end + mtspr 0x0b9,r4 + b ..ppcMtspr_any_end + mtspr 0x0ba,r4 + b ..ppcMtspr_any_end + mtspr 0x0bb,r4 + b ..ppcMtspr_any_end + mtspr 0x0bc,r4 + b ..ppcMtspr_any_end + mtspr 0x0bd,r4 + b ..ppcMtspr_any_end + mtspr 0x0be,r4 + b ..ppcMtspr_any_end + mtspr 0x0bf,r4 + b ..ppcMtspr_any_end + mtspr 0x0c0,r4 + b ..ppcMtspr_any_end + mtspr 0x0c1,r4 + b ..ppcMtspr_any_end + mtspr 0x0c2,r4 + b ..ppcMtspr_any_end + mtspr 0x0c3,r4 + b ..ppcMtspr_any_end + mtspr 0x0c4,r4 + b ..ppcMtspr_any_end + mtspr 0x0c5,r4 + b ..ppcMtspr_any_end + mtspr 0x0c6,r4 + b ..ppcMtspr_any_end + mtspr 0x0c7,r4 + b ..ppcMtspr_any_end + mtspr 0x0c8,r4 + b ..ppcMtspr_any_end + mtspr 0x0c9,r4 + b ..ppcMtspr_any_end + mtspr 0x0ca,r4 + b ..ppcMtspr_any_end + mtspr 0x0cb,r4 + b ..ppcMtspr_any_end + mtspr 0x0cc,r4 + b ..ppcMtspr_any_end + mtspr 0x0cd,r4 + b ..ppcMtspr_any_end + mtspr 0x0ce,r4 + b ..ppcMtspr_any_end + mtspr 0x0cf,r4 + b ..ppcMtspr_any_end + mtspr 0x0d0,r4 + b ..ppcMtspr_any_end + mtspr 0x0d1,r4 + b ..ppcMtspr_any_end + mtspr 0x0d2,r4 + b ..ppcMtspr_any_end + mtspr 0x0d3,r4 + b ..ppcMtspr_any_end + mtspr 0x0d4,r4 + b ..ppcMtspr_any_end + mtspr 0x0d5,r4 + b ..ppcMtspr_any_end + mtspr 0x0d6,r4 + b ..ppcMtspr_any_end + mtspr 0x0d7,r4 + b ..ppcMtspr_any_end + mtspr 0x0d8,r4 + b ..ppcMtspr_any_end + mtspr 0x0d9,r4 + b ..ppcMtspr_any_end + mtspr 0x0da,r4 + b ..ppcMtspr_any_end + mtspr 0x0db,r4 + b ..ppcMtspr_any_end + mtspr 0x0dc,r4 + b ..ppcMtspr_any_end + mtspr 0x0dd,r4 + b ..ppcMtspr_any_end + mtspr 0x0de,r4 + b ..ppcMtspr_any_end + mtspr 0x0df,r4 + b ..ppcMtspr_any_end + mtspr 0x0e0,r4 + b ..ppcMtspr_any_end + mtspr 0x0e1,r4 + b ..ppcMtspr_any_end + mtspr 0x0e2,r4 + b ..ppcMtspr_any_end + mtspr 0x0e3,r4 + b ..ppcMtspr_any_end + mtspr 0x0e4,r4 + b ..ppcMtspr_any_end + mtspr 0x0e5,r4 + b ..ppcMtspr_any_end + mtspr 0x0e6,r4 + b ..ppcMtspr_any_end + mtspr 0x0e7,r4 + b ..ppcMtspr_any_end + mtspr 0x0e8,r4 + b ..ppcMtspr_any_end + mtspr 0x0e9,r4 + b ..ppcMtspr_any_end + mtspr 0x0ea,r4 + b ..ppcMtspr_any_end + mtspr 0x0eb,r4 + b ..ppcMtspr_any_end + mtspr 0x0ec,r4 + b ..ppcMtspr_any_end + mtspr 0x0ed,r4 + b ..ppcMtspr_any_end + mtspr 0x0ee,r4 + b ..ppcMtspr_any_end + mtspr 0x0ef,r4 + b ..ppcMtspr_any_end + mtspr 0x0f0,r4 + b ..ppcMtspr_any_end + mtspr 0x0f1,r4 + b ..ppcMtspr_any_end + mtspr 0x0f2,r4 + b ..ppcMtspr_any_end + mtspr 0x0f3,r4 + b ..ppcMtspr_any_end + mtspr 0x0f4,r4 + b ..ppcMtspr_any_end + mtspr 0x0f5,r4 + b ..ppcMtspr_any_end + mtspr 0x0f6,r4 + b ..ppcMtspr_any_end + mtspr 0x0f7,r4 + b ..ppcMtspr_any_end + mtspr 0x0f8,r4 + b ..ppcMtspr_any_end + mtspr 0x0f9,r4 + b ..ppcMtspr_any_end + mtspr 0x0fa,r4 + b ..ppcMtspr_any_end + mtspr 0x0fb,r4 + b ..ppcMtspr_any_end + mtspr 0x0fc,r4 + b ..ppcMtspr_any_end + mtspr 0x0fd,r4 + b ..ppcMtspr_any_end + mtspr 0x0fe,r4 + b ..ppcMtspr_any_end + mtspr 0x0ff,r4 + b ..ppcMtspr_any_end + mtspr 0x100,r4 + b ..ppcMtspr_any_end + mtspr 0x101,r4 + b ..ppcMtspr_any_end + mtspr 0x102,r4 + b ..ppcMtspr_any_end + mtspr 0x103,r4 + b ..ppcMtspr_any_end + mtspr 0x104,r4 + b ..ppcMtspr_any_end + mtspr 0x105,r4 + b ..ppcMtspr_any_end + mtspr 0x106,r4 + b ..ppcMtspr_any_end + mtspr 0x107,r4 + b ..ppcMtspr_any_end + mtspr 0x108,r4 + b ..ppcMtspr_any_end + mtspr 0x109,r4 + b ..ppcMtspr_any_end + mtspr 0x10a,r4 + b ..ppcMtspr_any_end + mtspr 0x10b,r4 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + mtspr 0x10e,r4 + b ..ppcMtspr_any_end + mtspr 0x10f,r4 + b ..ppcMtspr_any_end + mtspr 0x110,r4 + b ..ppcMtspr_any_end + mtspr 0x111,r4 + b ..ppcMtspr_any_end + mtspr 0x112,r4 + b ..ppcMtspr_any_end + mtspr 0x113,r4 + b ..ppcMtspr_any_end + mtspr 0x114,r4 + b ..ppcMtspr_any_end + mtspr 0x115,r4 + b ..ppcMtspr_any_end + mtspr 0x116,r4 + b ..ppcMtspr_any_end + mtspr 0x117,r4 + b ..ppcMtspr_any_end + mtspr 0x118,r4 + b ..ppcMtspr_any_end + mtspr 0x119,r4 + b ..ppcMtspr_any_end + mtspr 0x11a,r4 + b ..ppcMtspr_any_end + mtspr 0x11b,r4 + b ..ppcMtspr_any_end + mtspr 0x11c,r4 + b ..ppcMtspr_any_end + mtspr 0x11d,r4 + b ..ppcMtspr_any_end + mtspr 0x11e,r4 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + mtspr 0x120,r4 + b ..ppcMtspr_any_end + mtspr 0x121,r4 + b ..ppcMtspr_any_end + mtspr 0x122,r4 + b ..ppcMtspr_any_end + mtspr 0x123,r4 + b ..ppcMtspr_any_end + mtspr 0x124,r4 + b ..ppcMtspr_any_end + mtspr 0x125,r4 + b ..ppcMtspr_any_end + mtspr 0x126,r4 + b ..ppcMtspr_any_end + mtspr 0x127,r4 + b ..ppcMtspr_any_end + mtspr 0x128,r4 + b ..ppcMtspr_any_end + mtspr 0x129,r4 + b ..ppcMtspr_any_end + mtspr 0x12a,r4 + b ..ppcMtspr_any_end + mtspr 0x12b,r4 + b ..ppcMtspr_any_end + mtspr 0x12c,r4 + b ..ppcMtspr_any_end + mtspr 0x12d,r4 + b ..ppcMtspr_any_end + mtspr 0x12e,r4 + b ..ppcMtspr_any_end + mtspr 0x12f,r4 + b ..ppcMtspr_any_end + mtspr 0x130,r4 + b ..ppcMtspr_any_end + mtspr 0x131,r4 + b ..ppcMtspr_any_end + mtspr 0x132,r4 + b ..ppcMtspr_any_end + mtspr 0x133,r4 + b ..ppcMtspr_any_end + mtspr 0x134,r4 + b ..ppcMtspr_any_end + mtspr 0x135,r4 + b ..ppcMtspr_any_end + mtspr 0x136,r4 + b ..ppcMtspr_any_end + mtspr 0x137,r4 + b ..ppcMtspr_any_end + mtspr 0x138,r4 + b ..ppcMtspr_any_end + mtspr 0x139,r4 + b ..ppcMtspr_any_end + mtspr 0x13a,r4 + b ..ppcMtspr_any_end + mtspr 0x13b,r4 + b ..ppcMtspr_any_end + mtspr 0x13c,r4 + b ..ppcMtspr_any_end + mtspr 0x13d,r4 + b ..ppcMtspr_any_end + mtspr 0x13e,r4 + b ..ppcMtspr_any_end + mtspr 0x13f,r4 + b ..ppcMtspr_any_end + mtspr 0x140,r4 + b ..ppcMtspr_any_end + mtspr 0x141,r4 + b ..ppcMtspr_any_end + mtspr 0x142,r4 + b ..ppcMtspr_any_end + mtspr 0x143,r4 + b ..ppcMtspr_any_end + mtspr 0x144,r4 + b ..ppcMtspr_any_end + mtspr 0x145,r4 + b ..ppcMtspr_any_end + mtspr 0x146,r4 + b ..ppcMtspr_any_end + mtspr 0x147,r4 + b ..ppcMtspr_any_end + mtspr 0x148,r4 + b ..ppcMtspr_any_end + mtspr 0x149,r4 + b ..ppcMtspr_any_end + mtspr 0x14a,r4 + b ..ppcMtspr_any_end + mtspr 0x14b,r4 + b ..ppcMtspr_any_end + mtspr 0x14c,r4 + b ..ppcMtspr_any_end + mtspr 0x14d,r4 + b ..ppcMtspr_any_end + mtspr 0x14e,r4 + b ..ppcMtspr_any_end + mtspr 0x14f,r4 + b ..ppcMtspr_any_end + mtspr 0x150,r4 + b ..ppcMtspr_any_end + mtspr 0x151,r4 + b ..ppcMtspr_any_end + mtspr 0x152,r4 + b ..ppcMtspr_any_end + mtspr 0x153,r4 + b ..ppcMtspr_any_end + mtspr 0x154,r4 + b ..ppcMtspr_any_end + mtspr 0x155,r4 + b ..ppcMtspr_any_end + mtspr 0x156,r4 + b ..ppcMtspr_any_end + mtspr 0x157,r4 + b ..ppcMtspr_any_end + mtspr 0x158,r4 + b ..ppcMtspr_any_end + mtspr 0x159,r4 + b ..ppcMtspr_any_end + mtspr 0x15a,r4 + b ..ppcMtspr_any_end + mtspr 0x15b,r4 + b ..ppcMtspr_any_end + mtspr 0x15c,r4 + b ..ppcMtspr_any_end + mtspr 0x15d,r4 + b ..ppcMtspr_any_end + mtspr 0x15e,r4 + b ..ppcMtspr_any_end + mtspr 0x15f,r4 + b ..ppcMtspr_any_end + mtspr 0x160,r4 + b ..ppcMtspr_any_end + mtspr 0x161,r4 + b ..ppcMtspr_any_end + mtspr 0x162,r4 + b ..ppcMtspr_any_end + mtspr 0x163,r4 + b ..ppcMtspr_any_end + mtspr 0x164,r4 + b ..ppcMtspr_any_end + mtspr 0x165,r4 + b ..ppcMtspr_any_end + mtspr 0x166,r4 + b ..ppcMtspr_any_end + mtspr 0x167,r4 + b ..ppcMtspr_any_end + mtspr 0x168,r4 + b ..ppcMtspr_any_end + mtspr 0x169,r4 + b ..ppcMtspr_any_end + mtspr 0x16a,r4 + b ..ppcMtspr_any_end + mtspr 0x16b,r4 + b ..ppcMtspr_any_end + mtspr 0x16c,r4 + b ..ppcMtspr_any_end + mtspr 0x16d,r4 + b ..ppcMtspr_any_end + mtspr 0x16e,r4 + b ..ppcMtspr_any_end + mtspr 0x16f,r4 + b ..ppcMtspr_any_end + mtspr 0x170,r4 + b ..ppcMtspr_any_end + mtspr 0x171,r4 + b ..ppcMtspr_any_end + mtspr 0x172,r4 + b ..ppcMtspr_any_end + mtspr 0x173,r4 + b ..ppcMtspr_any_end + mtspr 0x174,r4 + b ..ppcMtspr_any_end + mtspr 0x175,r4 + b ..ppcMtspr_any_end + mtspr 0x176,r4 + b ..ppcMtspr_any_end + mtspr 0x177,r4 + b ..ppcMtspr_any_end + mtspr 0x178,r4 + b ..ppcMtspr_any_end + mtspr 0x179,r4 + b ..ppcMtspr_any_end + mtspr 0x17a,r4 + b ..ppcMtspr_any_end + mtspr 0x17b,r4 + b ..ppcMtspr_any_end + mtspr 0x17c,r4 + b ..ppcMtspr_any_end + mtspr 0x17d,r4 + b ..ppcMtspr_any_end + mtspr 0x17e,r4 + b ..ppcMtspr_any_end + mtspr 0x17f,r4 + b ..ppcMtspr_any_end + mtspr 0x180,r4 + b ..ppcMtspr_any_end + mtspr 0x181,r4 + b ..ppcMtspr_any_end + mtspr 0x182,r4 + b ..ppcMtspr_any_end + mtspr 0x183,r4 + b ..ppcMtspr_any_end + mtspr 0x184,r4 + b ..ppcMtspr_any_end + mtspr 0x185,r4 + b ..ppcMtspr_any_end + mtspr 0x186,r4 + b ..ppcMtspr_any_end + mtspr 0x187,r4 + b ..ppcMtspr_any_end + mtspr 0x188,r4 + b ..ppcMtspr_any_end + mtspr 0x189,r4 + b ..ppcMtspr_any_end + mtspr 0x18a,r4 + b ..ppcMtspr_any_end + mtspr 0x18b,r4 + b ..ppcMtspr_any_end + mtspr 0x18c,r4 + b ..ppcMtspr_any_end + mtspr 0x18d,r4 + b ..ppcMtspr_any_end + mtspr 0x18e,r4 + b ..ppcMtspr_any_end + mtspr 0x18f,r4 + b ..ppcMtspr_any_end + mtspr 0x190,r4 + b ..ppcMtspr_any_end + mtspr 0x191,r4 + b ..ppcMtspr_any_end + mtspr 0x192,r4 + b ..ppcMtspr_any_end + mtspr 0x193,r4 + b ..ppcMtspr_any_end + mtspr 0x194,r4 + b ..ppcMtspr_any_end + mtspr 0x195,r4 + b ..ppcMtspr_any_end + mtspr 0x196,r4 + b ..ppcMtspr_any_end + mtspr 0x197,r4 + b ..ppcMtspr_any_end + mtspr 0x198,r4 + b ..ppcMtspr_any_end + mtspr 0x199,r4 + b ..ppcMtspr_any_end + mtspr 0x19a,r4 + b ..ppcMtspr_any_end + mtspr 0x19b,r4 + b ..ppcMtspr_any_end + mtspr 0x19c,r4 + b ..ppcMtspr_any_end + mtspr 0x19d,r4 + b ..ppcMtspr_any_end + mtspr 0x19e,r4 + b ..ppcMtspr_any_end + mtspr 0x19f,r4 + b ..ppcMtspr_any_end + mtspr 0x1a0,r4 + b ..ppcMtspr_any_end + mtspr 0x1a1,r4 + b ..ppcMtspr_any_end + mtspr 0x1a2,r4 + b ..ppcMtspr_any_end + mtspr 0x1a3,r4 + b ..ppcMtspr_any_end + mtspr 0x1a4,r4 + b ..ppcMtspr_any_end + mtspr 0x1a5,r4 + b ..ppcMtspr_any_end + mtspr 0x1a6,r4 + b ..ppcMtspr_any_end + mtspr 0x1a7,r4 + b ..ppcMtspr_any_end + mtspr 0x1a8,r4 + b ..ppcMtspr_any_end + mtspr 0x1a9,r4 + b ..ppcMtspr_any_end + mtspr 0x1aa,r4 + b ..ppcMtspr_any_end + mtspr 0x1ab,r4 + b ..ppcMtspr_any_end + mtspr 0x1ac,r4 + b ..ppcMtspr_any_end + mtspr 0x1ad,r4 + b ..ppcMtspr_any_end + mtspr 0x1ae,r4 + b ..ppcMtspr_any_end + mtspr 0x1af,r4 + b ..ppcMtspr_any_end + mtspr 0x1b0,r4 + b ..ppcMtspr_any_end + mtspr 0x1b1,r4 + b ..ppcMtspr_any_end + mtspr 0x1b2,r4 + b ..ppcMtspr_any_end + mtspr 0x1b3,r4 + b ..ppcMtspr_any_end + mtspr 0x1b4,r4 + b ..ppcMtspr_any_end + mtspr 0x1b5,r4 + b ..ppcMtspr_any_end + mtspr 0x1b6,r4 + b ..ppcMtspr_any_end + mtspr 0x1b7,r4 + b ..ppcMtspr_any_end + mtspr 0x1b8,r4 + b ..ppcMtspr_any_end + mtspr 0x1b9,r4 + b ..ppcMtspr_any_end + mtspr 0x1ba,r4 + b ..ppcMtspr_any_end + mtspr 0x1bb,r4 + b ..ppcMtspr_any_end + mtspr 0x1bc,r4 + b ..ppcMtspr_any_end + mtspr 0x1bd,r4 + b ..ppcMtspr_any_end + mtspr 0x1be,r4 + b ..ppcMtspr_any_end + mtspr 0x1bf,r4 + b ..ppcMtspr_any_end + mtspr 0x1c0,r4 + b ..ppcMtspr_any_end + mtspr 0x1c1,r4 + b ..ppcMtspr_any_end + mtspr 0x1c2,r4 + b ..ppcMtspr_any_end + mtspr 0x1c3,r4 + b ..ppcMtspr_any_end + mtspr 0x1c4,r4 + b ..ppcMtspr_any_end + mtspr 0x1c5,r4 + b ..ppcMtspr_any_end + mtspr 0x1c6,r4 + b ..ppcMtspr_any_end + mtspr 0x1c7,r4 + b ..ppcMtspr_any_end + mtspr 0x1c8,r4 + b ..ppcMtspr_any_end + mtspr 0x1c9,r4 + b ..ppcMtspr_any_end + mtspr 0x1ca,r4 + b ..ppcMtspr_any_end + mtspr 0x1cb,r4 + b ..ppcMtspr_any_end + mtspr 0x1cc,r4 + b ..ppcMtspr_any_end + mtspr 0x1cd,r4 + b ..ppcMtspr_any_end + mtspr 0x1ce,r4 + b ..ppcMtspr_any_end + mtspr 0x1cf,r4 + b ..ppcMtspr_any_end + mtspr 0x1d0,r4 + b ..ppcMtspr_any_end + mtspr 0x1d1,r4 + b ..ppcMtspr_any_end + mtspr 0x1d2,r4 + b ..ppcMtspr_any_end + mtspr 0x1d3,r4 + b ..ppcMtspr_any_end + mtspr 0x1d4,r4 + b ..ppcMtspr_any_end + mtspr 0x1d5,r4 + b ..ppcMtspr_any_end + mtspr 0x1d6,r4 + b ..ppcMtspr_any_end + mtspr 0x1d7,r4 + b ..ppcMtspr_any_end + mtspr 0x1d8,r4 + b ..ppcMtspr_any_end + mtspr 0x1d9,r4 + b ..ppcMtspr_any_end + mtspr 0x1da,r4 + b ..ppcMtspr_any_end + mtspr 0x1db,r4 + b ..ppcMtspr_any_end + mtspr 0x1dc,r4 + b ..ppcMtspr_any_end + mtspr 0x1dd,r4 + b ..ppcMtspr_any_end + mtspr 0x1de,r4 + b ..ppcMtspr_any_end + mtspr 0x1df,r4 + b ..ppcMtspr_any_end + mtspr 0x1e0,r4 + b ..ppcMtspr_any_end + mtspr 0x1e1,r4 + b ..ppcMtspr_any_end + mtspr 0x1e2,r4 + b ..ppcMtspr_any_end + mtspr 0x1e3,r4 + b ..ppcMtspr_any_end + mtspr 0x1e4,r4 + b ..ppcMtspr_any_end + mtspr 0x1e5,r4 + b ..ppcMtspr_any_end + mtspr 0x1e6,r4 + b ..ppcMtspr_any_end + mtspr 0x1e7,r4 + b ..ppcMtspr_any_end + mtspr 0x1e8,r4 + b ..ppcMtspr_any_end + mtspr 0x1e9,r4 + b ..ppcMtspr_any_end + mtspr 0x1ea,r4 + b ..ppcMtspr_any_end + mtspr 0x1eb,r4 + b ..ppcMtspr_any_end + mtspr 0x1ec,r4 + b ..ppcMtspr_any_end + mtspr 0x1ed,r4 + b ..ppcMtspr_any_end + mtspr 0x1ee,r4 + b ..ppcMtspr_any_end + mtspr 0x1ef,r4 + b ..ppcMtspr_any_end + mtspr 0x1f0,r4 + b ..ppcMtspr_any_end + mtspr 0x1f1,r4 + b ..ppcMtspr_any_end + mtspr 0x1f2,r4 + b ..ppcMtspr_any_end + mtspr 0x1f3,r4 + b ..ppcMtspr_any_end + mtspr 0x1f4,r4 + b ..ppcMtspr_any_end + mtspr 0x1f5,r4 + b ..ppcMtspr_any_end + mtspr 0x1f6,r4 + b ..ppcMtspr_any_end + mtspr 0x1f7,r4 + b ..ppcMtspr_any_end + mtspr 0x1f8,r4 + b ..ppcMtspr_any_end + mtspr 0x1f9,r4 + b ..ppcMtspr_any_end + mtspr 0x1fa,r4 + b ..ppcMtspr_any_end + mtspr 0x1fb,r4 + b ..ppcMtspr_any_end + mtspr 0x1fc,r4 + b ..ppcMtspr_any_end + mtspr 0x1fd,r4 + b ..ppcMtspr_any_end + mtspr 0x1fe,r4 + b ..ppcMtspr_any_end + mtspr 0x1ff,r4 + b ..ppcMtspr_any_end + mtspr 0x200,r4 + b ..ppcMtspr_any_end + mtspr 0x201,r4 + b ..ppcMtspr_any_end + mtspr 0x202,r4 + b ..ppcMtspr_any_end + mtspr 0x203,r4 + b ..ppcMtspr_any_end + mtspr 0x204,r4 + b ..ppcMtspr_any_end + mtspr 0x205,r4 + b ..ppcMtspr_any_end + mtspr 0x206,r4 + b ..ppcMtspr_any_end + mtspr 0x207,r4 + b ..ppcMtspr_any_end + mtspr 0x208,r4 + b ..ppcMtspr_any_end + mtspr 0x209,r4 + b ..ppcMtspr_any_end + mtspr 0x20a,r4 + b ..ppcMtspr_any_end + mtspr 0x20b,r4 + b ..ppcMtspr_any_end + mtspr 0x20c,r4 + b ..ppcMtspr_any_end + mtspr 0x20d,r4 + b ..ppcMtspr_any_end + mtspr 0x20e,r4 + b ..ppcMtspr_any_end + mtspr 0x20f,r4 + b ..ppcMtspr_any_end + mtspr 0x210,r4 + b ..ppcMtspr_any_end + mtspr 0x211,r4 + b ..ppcMtspr_any_end + mtspr 0x212,r4 + b ..ppcMtspr_any_end + mtspr 0x213,r4 + b ..ppcMtspr_any_end + mtspr 0x214,r4 + b ..ppcMtspr_any_end + mtspr 0x215,r4 + b ..ppcMtspr_any_end + mtspr 0x216,r4 + b ..ppcMtspr_any_end + mtspr 0x217,r4 + b ..ppcMtspr_any_end + mtspr 0x218,r4 + b ..ppcMtspr_any_end + mtspr 0x219,r4 + b ..ppcMtspr_any_end + mtspr 0x21a,r4 + b ..ppcMtspr_any_end + mtspr 0x21b,r4 + b ..ppcMtspr_any_end + mtspr 0x21c,r4 + b ..ppcMtspr_any_end + mtspr 0x21d,r4 + b ..ppcMtspr_any_end + mtspr 0x21e,r4 + b ..ppcMtspr_any_end + mtspr 0x21f,r4 + b ..ppcMtspr_any_end + mtspr 0x220,r4 + b ..ppcMtspr_any_end + mtspr 0x221,r4 + b ..ppcMtspr_any_end + mtspr 0x222,r4 + b ..ppcMtspr_any_end + mtspr 0x223,r4 + b ..ppcMtspr_any_end + mtspr 0x224,r4 + b ..ppcMtspr_any_end + mtspr 0x225,r4 + b ..ppcMtspr_any_end + mtspr 0x226,r4 + b ..ppcMtspr_any_end + mtspr 0x227,r4 + b ..ppcMtspr_any_end + mtspr 0x228,r4 + b ..ppcMtspr_any_end + mtspr 0x229,r4 + b ..ppcMtspr_any_end + mtspr 0x22a,r4 + b ..ppcMtspr_any_end + mtspr 0x22b,r4 + b ..ppcMtspr_any_end + mtspr 0x22c,r4 + b ..ppcMtspr_any_end + mtspr 0x22d,r4 + b ..ppcMtspr_any_end + mtspr 0x22e,r4 + b ..ppcMtspr_any_end + mtspr 0x22f,r4 + b ..ppcMtspr_any_end + mtspr 0x230,r4 + b ..ppcMtspr_any_end + mtspr 0x231,r4 + b ..ppcMtspr_any_end + mtspr 0x232,r4 + b ..ppcMtspr_any_end + mtspr 0x233,r4 + b ..ppcMtspr_any_end + mtspr 0x234,r4 + b ..ppcMtspr_any_end + mtspr 0x235,r4 + b ..ppcMtspr_any_end + mtspr 0x236,r4 + b ..ppcMtspr_any_end + mtspr 0x237,r4 + b ..ppcMtspr_any_end + mtspr 0x238,r4 + b ..ppcMtspr_any_end + mtspr 0x239,r4 + b ..ppcMtspr_any_end + mtspr 0x23a,r4 + b ..ppcMtspr_any_end + mtspr 0x23b,r4 + b ..ppcMtspr_any_end + mtspr 0x23c,r4 + b ..ppcMtspr_any_end + mtspr 0x23d,r4 + b ..ppcMtspr_any_end + mtspr 0x23e,r4 + b ..ppcMtspr_any_end + mtspr 0x23f,r4 + b ..ppcMtspr_any_end + mtspr 0x240,r4 + b ..ppcMtspr_any_end + mtspr 0x241,r4 + b ..ppcMtspr_any_end + mtspr 0x242,r4 + b ..ppcMtspr_any_end + mtspr 0x243,r4 + b ..ppcMtspr_any_end + mtspr 0x244,r4 + b ..ppcMtspr_any_end + mtspr 0x245,r4 + b ..ppcMtspr_any_end + mtspr 0x246,r4 + b ..ppcMtspr_any_end + mtspr 0x247,r4 + b ..ppcMtspr_any_end + mtspr 0x248,r4 + b ..ppcMtspr_any_end + mtspr 0x249,r4 + b ..ppcMtspr_any_end + mtspr 0x24a,r4 + b ..ppcMtspr_any_end + mtspr 0x24b,r4 + b ..ppcMtspr_any_end + mtspr 0x24c,r4 + b ..ppcMtspr_any_end + mtspr 0x24d,r4 + b ..ppcMtspr_any_end + mtspr 0x24e,r4 + b ..ppcMtspr_any_end + mtspr 0x24f,r4 + b ..ppcMtspr_any_end + mtspr 0x250,r4 + b ..ppcMtspr_any_end + mtspr 0x251,r4 + b ..ppcMtspr_any_end + mtspr 0x252,r4 + b ..ppcMtspr_any_end + mtspr 0x253,r4 + b ..ppcMtspr_any_end + mtspr 0x254,r4 + b ..ppcMtspr_any_end + mtspr 0x255,r4 + b ..ppcMtspr_any_end + mtspr 0x256,r4 + b ..ppcMtspr_any_end + mtspr 0x257,r4 + b ..ppcMtspr_any_end + mtspr 0x258,r4 + b ..ppcMtspr_any_end + mtspr 0x259,r4 + b ..ppcMtspr_any_end + mtspr 0x25a,r4 + b ..ppcMtspr_any_end + mtspr 0x25b,r4 + b ..ppcMtspr_any_end + mtspr 0x25c,r4 + b ..ppcMtspr_any_end + mtspr 0x25d,r4 + b ..ppcMtspr_any_end + mtspr 0x25e,r4 + b ..ppcMtspr_any_end + mtspr 0x25f,r4 + b ..ppcMtspr_any_end + mtspr 0x260,r4 + b ..ppcMtspr_any_end + mtspr 0x261,r4 + b ..ppcMtspr_any_end + mtspr 0x262,r4 + b ..ppcMtspr_any_end + mtspr 0x263,r4 + b ..ppcMtspr_any_end + mtspr 0x264,r4 + b ..ppcMtspr_any_end + mtspr 0x265,r4 + b ..ppcMtspr_any_end + mtspr 0x266,r4 + b ..ppcMtspr_any_end + mtspr 0x267,r4 + b ..ppcMtspr_any_end + mtspr 0x268,r4 + b ..ppcMtspr_any_end + mtspr 0x269,r4 + b ..ppcMtspr_any_end + mtspr 0x26a,r4 + b ..ppcMtspr_any_end + mtspr 0x26b,r4 + b ..ppcMtspr_any_end + mtspr 0x26c,r4 + b ..ppcMtspr_any_end + mtspr 0x26d,r4 + b ..ppcMtspr_any_end + mtspr 0x26e,r4 + b ..ppcMtspr_any_end + mtspr 0x26f,r4 + b ..ppcMtspr_any_end + mtspr 0x270,r4 + b ..ppcMtspr_any_end + mtspr 0x271,r4 + b ..ppcMtspr_any_end + mtspr 0x272,r4 + b ..ppcMtspr_any_end + mtspr 0x273,r4 + b ..ppcMtspr_any_end + mtspr 0x274,r4 + b ..ppcMtspr_any_end + mtspr 0x275,r4 + b ..ppcMtspr_any_end + mtspr 0x276,r4 + b ..ppcMtspr_any_end + mtspr 0x277,r4 + b ..ppcMtspr_any_end + mtspr 0x278,r4 + b ..ppcMtspr_any_end + mtspr 0x279,r4 + b ..ppcMtspr_any_end + mtspr 0x27a,r4 + b ..ppcMtspr_any_end + mtspr 0x27b,r4 + b ..ppcMtspr_any_end + mtspr 0x27c,r4 + b ..ppcMtspr_any_end + mtspr 0x27d,r4 + b ..ppcMtspr_any_end + mtspr 0x27e,r4 + b ..ppcMtspr_any_end + mtspr 0x27f,r4 + b ..ppcMtspr_any_end + mtspr 0x280,r4 + b ..ppcMtspr_any_end + mtspr 0x281,r4 + b ..ppcMtspr_any_end + mtspr 0x282,r4 + b ..ppcMtspr_any_end + mtspr 0x283,r4 + b ..ppcMtspr_any_end + mtspr 0x284,r4 + b ..ppcMtspr_any_end + mtspr 0x285,r4 + b ..ppcMtspr_any_end + mtspr 0x286,r4 + b ..ppcMtspr_any_end + mtspr 0x287,r4 + b ..ppcMtspr_any_end + mtspr 0x288,r4 + b ..ppcMtspr_any_end + mtspr 0x289,r4 + b ..ppcMtspr_any_end + mtspr 0x28a,r4 + b ..ppcMtspr_any_end + mtspr 0x28b,r4 + b ..ppcMtspr_any_end + mtspr 0x28c,r4 + b ..ppcMtspr_any_end + mtspr 0x28d,r4 + b ..ppcMtspr_any_end + mtspr 0x28e,r4 + b ..ppcMtspr_any_end + mtspr 0x28f,r4 + b ..ppcMtspr_any_end + mtspr 0x290,r4 + b ..ppcMtspr_any_end + mtspr 0x291,r4 + b ..ppcMtspr_any_end + mtspr 0x292,r4 + b ..ppcMtspr_any_end + mtspr 0x293,r4 + b ..ppcMtspr_any_end + mtspr 0x294,r4 + b ..ppcMtspr_any_end + mtspr 0x295,r4 + b ..ppcMtspr_any_end + mtspr 0x296,r4 + b ..ppcMtspr_any_end + mtspr 0x297,r4 + b ..ppcMtspr_any_end + mtspr 0x298,r4 + b ..ppcMtspr_any_end + mtspr 0x299,r4 + b ..ppcMtspr_any_end + mtspr 0x29a,r4 + b ..ppcMtspr_any_end + mtspr 0x29b,r4 + b ..ppcMtspr_any_end + mtspr 0x29c,r4 + b ..ppcMtspr_any_end + mtspr 0x29d,r4 + b ..ppcMtspr_any_end + mtspr 0x29e,r4 + b ..ppcMtspr_any_end + mtspr 0x29f,r4 + b ..ppcMtspr_any_end + mtspr 0x2a0,r4 + b ..ppcMtspr_any_end + mtspr 0x2a1,r4 + b ..ppcMtspr_any_end + mtspr 0x2a2,r4 + b ..ppcMtspr_any_end + mtspr 0x2a3,r4 + b ..ppcMtspr_any_end + mtspr 0x2a4,r4 + b ..ppcMtspr_any_end + mtspr 0x2a5,r4 + b ..ppcMtspr_any_end + mtspr 0x2a6,r4 + b ..ppcMtspr_any_end + mtspr 0x2a7,r4 + b ..ppcMtspr_any_end + mtspr 0x2a8,r4 + b ..ppcMtspr_any_end + mtspr 0x2a9,r4 + b ..ppcMtspr_any_end + mtspr 0x2aa,r4 + b ..ppcMtspr_any_end + mtspr 0x2ab,r4 + b ..ppcMtspr_any_end + mtspr 0x2ac,r4 + b ..ppcMtspr_any_end + mtspr 0x2ad,r4 + b ..ppcMtspr_any_end + mtspr 0x2ae,r4 + b ..ppcMtspr_any_end + mtspr 0x2af,r4 + b ..ppcMtspr_any_end + mtspr 0x2b0,r4 + b ..ppcMtspr_any_end + mtspr 0x2b1,r4 + b ..ppcMtspr_any_end + mtspr 0x2b2,r4 + b ..ppcMtspr_any_end + mtspr 0x2b3,r4 + b ..ppcMtspr_any_end + mtspr 0x2b4,r4 + b ..ppcMtspr_any_end + mtspr 0x2b5,r4 + b ..ppcMtspr_any_end + mtspr 0x2b6,r4 + b ..ppcMtspr_any_end + mtspr 0x2b7,r4 + b ..ppcMtspr_any_end + mtspr 0x2b8,r4 + b ..ppcMtspr_any_end + mtspr 0x2b9,r4 + b ..ppcMtspr_any_end + mtspr 0x2ba,r4 + b ..ppcMtspr_any_end + mtspr 0x2bb,r4 + b ..ppcMtspr_any_end + mtspr 0x2bc,r4 + b ..ppcMtspr_any_end + mtspr 0x2bd,r4 + b ..ppcMtspr_any_end + mtspr 0x2be,r4 + b ..ppcMtspr_any_end + mtspr 0x2bf,r4 + b ..ppcMtspr_any_end + mtspr 0x2c0,r4 + b ..ppcMtspr_any_end + mtspr 0x2c1,r4 + b ..ppcMtspr_any_end + mtspr 0x2c2,r4 + b ..ppcMtspr_any_end + mtspr 0x2c3,r4 + b ..ppcMtspr_any_end + mtspr 0x2c4,r4 + b ..ppcMtspr_any_end + mtspr 0x2c5,r4 + b ..ppcMtspr_any_end + mtspr 0x2c6,r4 + b ..ppcMtspr_any_end + mtspr 0x2c7,r4 + b ..ppcMtspr_any_end + mtspr 0x2c8,r4 + b ..ppcMtspr_any_end + mtspr 0x2c9,r4 + b ..ppcMtspr_any_end + mtspr 0x2ca,r4 + b ..ppcMtspr_any_end + mtspr 0x2cb,r4 + b ..ppcMtspr_any_end + mtspr 0x2cc,r4 + b ..ppcMtspr_any_end + mtspr 0x2cd,r4 + b ..ppcMtspr_any_end + mtspr 0x2ce,r4 + b ..ppcMtspr_any_end + mtspr 0x2cf,r4 + b ..ppcMtspr_any_end + mtspr 0x2d0,r4 + b ..ppcMtspr_any_end + mtspr 0x2d1,r4 + b ..ppcMtspr_any_end + mtspr 0x2d2,r4 + b ..ppcMtspr_any_end + mtspr 0x2d3,r4 + b ..ppcMtspr_any_end + mtspr 0x2d4,r4 + b ..ppcMtspr_any_end + mtspr 0x2d5,r4 + b ..ppcMtspr_any_end + mtspr 0x2d6,r4 + b ..ppcMtspr_any_end + mtspr 0x2d7,r4 + b ..ppcMtspr_any_end + mtspr 0x2d8,r4 + b ..ppcMtspr_any_end + mtspr 0x2d9,r4 + b ..ppcMtspr_any_end + mtspr 0x2da,r4 + b ..ppcMtspr_any_end + mtspr 0x2db,r4 + b ..ppcMtspr_any_end + mtspr 0x2dc,r4 + b ..ppcMtspr_any_end + mtspr 0x2dd,r4 + b ..ppcMtspr_any_end + mtspr 0x2de,r4 + b ..ppcMtspr_any_end + mtspr 0x2df,r4 + b ..ppcMtspr_any_end + mtspr 0x2e0,r4 + b ..ppcMtspr_any_end + mtspr 0x2e1,r4 + b ..ppcMtspr_any_end + mtspr 0x2e2,r4 + b ..ppcMtspr_any_end + mtspr 0x2e3,r4 + b ..ppcMtspr_any_end + mtspr 0x2e4,r4 + b ..ppcMtspr_any_end + mtspr 0x2e5,r4 + b ..ppcMtspr_any_end + mtspr 0x2e6,r4 + b ..ppcMtspr_any_end + mtspr 0x2e7,r4 + b ..ppcMtspr_any_end + mtspr 0x2e8,r4 + b ..ppcMtspr_any_end + mtspr 0x2e9,r4 + b ..ppcMtspr_any_end + mtspr 0x2ea,r4 + b ..ppcMtspr_any_end + mtspr 0x2eb,r4 + b ..ppcMtspr_any_end + mtspr 0x2ec,r4 + b ..ppcMtspr_any_end + mtspr 0x2ed,r4 + b ..ppcMtspr_any_end + mtspr 0x2ee,r4 + b ..ppcMtspr_any_end + mtspr 0x2ef,r4 + b ..ppcMtspr_any_end + mtspr 0x2f0,r4 + b ..ppcMtspr_any_end + mtspr 0x2f1,r4 + b ..ppcMtspr_any_end + mtspr 0x2f2,r4 + b ..ppcMtspr_any_end + mtspr 0x2f3,r4 + b ..ppcMtspr_any_end + mtspr 0x2f4,r4 + b ..ppcMtspr_any_end + mtspr 0x2f5,r4 + b ..ppcMtspr_any_end + mtspr 0x2f6,r4 + b ..ppcMtspr_any_end + mtspr 0x2f7,r4 + b ..ppcMtspr_any_end + mtspr 0x2f8,r4 + b ..ppcMtspr_any_end + mtspr 0x2f9,r4 + b ..ppcMtspr_any_end + mtspr 0x2fa,r4 + b ..ppcMtspr_any_end + mtspr 0x2fb,r4 + b ..ppcMtspr_any_end + mtspr 0x2fc,r4 + b ..ppcMtspr_any_end + mtspr 0x2fd,r4 + b ..ppcMtspr_any_end + mtspr 0x2fe,r4 + b ..ppcMtspr_any_end + mtspr 0x2ff,r4 + b ..ppcMtspr_any_end + mtspr 0x300,r4 + b ..ppcMtspr_any_end + mtspr 0x301,r4 + b ..ppcMtspr_any_end + mtspr 0x302,r4 + b ..ppcMtspr_any_end + mtspr 0x303,r4 + b ..ppcMtspr_any_end + mtspr 0x304,r4 + b ..ppcMtspr_any_end + mtspr 0x305,r4 + b ..ppcMtspr_any_end + mtspr 0x306,r4 + b ..ppcMtspr_any_end + mtspr 0x307,r4 + b ..ppcMtspr_any_end + mtspr 0x308,r4 + b ..ppcMtspr_any_end + mtspr 0x309,r4 + b ..ppcMtspr_any_end + mtspr 0x30a,r4 + b ..ppcMtspr_any_end + mtspr 0x30b,r4 + b ..ppcMtspr_any_end + mtspr 0x30c,r4 + b ..ppcMtspr_any_end + mtspr 0x30d,r4 + b ..ppcMtspr_any_end + mtspr 0x30e,r4 + b ..ppcMtspr_any_end + mtspr 0x30f,r4 + b ..ppcMtspr_any_end + mtspr 0x310,r4 + b ..ppcMtspr_any_end + mtspr 0x311,r4 + b ..ppcMtspr_any_end + mtspr 0x312,r4 + b ..ppcMtspr_any_end + mtspr 0x313,r4 + b ..ppcMtspr_any_end + mtspr 0x314,r4 + b ..ppcMtspr_any_end + mtspr 0x315,r4 + b ..ppcMtspr_any_end + mtspr 0x316,r4 + b ..ppcMtspr_any_end + mtspr 0x317,r4 + b ..ppcMtspr_any_end + mtspr 0x318,r4 + b ..ppcMtspr_any_end + mtspr 0x319,r4 + b ..ppcMtspr_any_end + mtspr 0x31a,r4 + b ..ppcMtspr_any_end + mtspr 0x31b,r4 + b ..ppcMtspr_any_end + mtspr 0x31c,r4 + b ..ppcMtspr_any_end + mtspr 0x31d,r4 + b ..ppcMtspr_any_end + mtspr 0x31e,r4 + b ..ppcMtspr_any_end + mtspr 0x31f,r4 + b ..ppcMtspr_any_end + mtspr 0x320,r4 + b ..ppcMtspr_any_end + mtspr 0x321,r4 + b ..ppcMtspr_any_end + mtspr 0x322,r4 + b ..ppcMtspr_any_end + mtspr 0x323,r4 + b ..ppcMtspr_any_end + mtspr 0x324,r4 + b ..ppcMtspr_any_end + mtspr 0x325,r4 + b ..ppcMtspr_any_end + mtspr 0x326,r4 + b ..ppcMtspr_any_end + mtspr 0x327,r4 + b ..ppcMtspr_any_end + mtspr 0x328,r4 + b ..ppcMtspr_any_end + mtspr 0x329,r4 + b ..ppcMtspr_any_end + mtspr 0x32a,r4 + b ..ppcMtspr_any_end + mtspr 0x32b,r4 + b ..ppcMtspr_any_end + mtspr 0x32c,r4 + b ..ppcMtspr_any_end + mtspr 0x32d,r4 + b ..ppcMtspr_any_end + mtspr 0x32e,r4 + b ..ppcMtspr_any_end + mtspr 0x32f,r4 + b ..ppcMtspr_any_end + mtspr 0x330,r4 + b ..ppcMtspr_any_end + mtspr 0x331,r4 + b ..ppcMtspr_any_end + mtspr 0x332,r4 + b ..ppcMtspr_any_end + mtspr 0x333,r4 + b ..ppcMtspr_any_end + mtspr 0x334,r4 + b ..ppcMtspr_any_end + mtspr 0x335,r4 + b ..ppcMtspr_any_end + mtspr 0x336,r4 + b ..ppcMtspr_any_end + mtspr 0x337,r4 + b ..ppcMtspr_any_end + mtspr 0x338,r4 + b ..ppcMtspr_any_end + mtspr 0x339,r4 + b ..ppcMtspr_any_end + mtspr 0x33a,r4 + b ..ppcMtspr_any_end + mtspr 0x33b,r4 + b ..ppcMtspr_any_end + mtspr 0x33c,r4 + b ..ppcMtspr_any_end + mtspr 0x33d,r4 + b ..ppcMtspr_any_end + mtspr 0x33e,r4 + b ..ppcMtspr_any_end + mtspr 0x33f,r4 + b ..ppcMtspr_any_end + mtspr 0x340,r4 + b ..ppcMtspr_any_end + mtspr 0x341,r4 + b ..ppcMtspr_any_end + mtspr 0x342,r4 + b ..ppcMtspr_any_end + mtspr 0x343,r4 + b ..ppcMtspr_any_end + mtspr 0x344,r4 + b ..ppcMtspr_any_end + mtspr 0x345,r4 + b ..ppcMtspr_any_end + mtspr 0x346,r4 + b ..ppcMtspr_any_end + mtspr 0x347,r4 + b ..ppcMtspr_any_end + mtspr 0x348,r4 + b ..ppcMtspr_any_end + mtspr 0x349,r4 + b ..ppcMtspr_any_end + mtspr 0x34a,r4 + b ..ppcMtspr_any_end + mtspr 0x34b,r4 + b ..ppcMtspr_any_end + mtspr 0x34c,r4 + b ..ppcMtspr_any_end + mtspr 0x34d,r4 + b ..ppcMtspr_any_end + mtspr 0x34e,r4 + b ..ppcMtspr_any_end + mtspr 0x34f,r4 + b ..ppcMtspr_any_end + mtspr 0x350,r4 + b ..ppcMtspr_any_end + mtspr 0x351,r4 + b ..ppcMtspr_any_end + mtspr 0x352,r4 + b ..ppcMtspr_any_end + mtspr 0x353,r4 + b ..ppcMtspr_any_end + mtspr 0x354,r4 + b ..ppcMtspr_any_end + mtspr 0x355,r4 + b ..ppcMtspr_any_end + mtspr 0x356,r4 + b ..ppcMtspr_any_end + mtspr 0x357,r4 + b ..ppcMtspr_any_end + mtspr 0x358,r4 + b ..ppcMtspr_any_end + mtspr 0x359,r4 + b ..ppcMtspr_any_end + mtspr 0x35a,r4 + b ..ppcMtspr_any_end + mtspr 0x35b,r4 + b ..ppcMtspr_any_end + mtspr 0x35c,r4 + b ..ppcMtspr_any_end + mtspr 0x35d,r4 + b ..ppcMtspr_any_end + mtspr 0x35e,r4 + b ..ppcMtspr_any_end + mtspr 0x35f,r4 + b ..ppcMtspr_any_end + mtspr 0x360,r4 + b ..ppcMtspr_any_end + mtspr 0x361,r4 + b ..ppcMtspr_any_end + mtspr 0x362,r4 + b ..ppcMtspr_any_end + mtspr 0x363,r4 + b ..ppcMtspr_any_end + mtspr 0x364,r4 + b ..ppcMtspr_any_end + mtspr 0x365,r4 + b ..ppcMtspr_any_end + mtspr 0x366,r4 + b ..ppcMtspr_any_end + mtspr 0x367,r4 + b ..ppcMtspr_any_end + mtspr 0x368,r4 + b ..ppcMtspr_any_end + mtspr 0x369,r4 + b ..ppcMtspr_any_end + mtspr 0x36a,r4 + b ..ppcMtspr_any_end + mtspr 0x36b,r4 + b ..ppcMtspr_any_end + mtspr 0x36c,r4 + b ..ppcMtspr_any_end + mtspr 0x36d,r4 + b ..ppcMtspr_any_end + mtspr 0x36e,r4 + b ..ppcMtspr_any_end + mtspr 0x36f,r4 + b ..ppcMtspr_any_end + mtspr 0x370,r4 + b ..ppcMtspr_any_end + mtspr 0x371,r4 + b ..ppcMtspr_any_end + mtspr 0x372,r4 + b ..ppcMtspr_any_end + mtspr 0x373,r4 + b ..ppcMtspr_any_end + mtspr 0x374,r4 + b ..ppcMtspr_any_end + mtspr 0x375,r4 + b ..ppcMtspr_any_end + mtspr 0x376,r4 + b ..ppcMtspr_any_end + mtspr 0x377,r4 + b ..ppcMtspr_any_end + mtspr 0x378,r4 + b ..ppcMtspr_any_end + mtspr 0x379,r4 + b ..ppcMtspr_any_end + mtspr 0x37a,r4 + b ..ppcMtspr_any_end + mtspr 0x37b,r4 + b ..ppcMtspr_any_end + mtspr 0x37c,r4 + b ..ppcMtspr_any_end + mtspr 0x37d,r4 + b ..ppcMtspr_any_end + mtspr 0x37e,r4 + b ..ppcMtspr_any_end + mtspr 0x37f,r4 + b ..ppcMtspr_any_end + mtspr 0x380,r4 + b ..ppcMtspr_any_end + mtspr 0x381,r4 + b ..ppcMtspr_any_end + mtspr 0x382,r4 + b ..ppcMtspr_any_end + mtspr 0x383,r4 + b ..ppcMtspr_any_end + mtspr 0x384,r4 + b ..ppcMtspr_any_end + mtspr 0x385,r4 + b ..ppcMtspr_any_end + mtspr 0x386,r4 + b ..ppcMtspr_any_end + mtspr 0x387,r4 + b ..ppcMtspr_any_end + mtspr 0x388,r4 + b ..ppcMtspr_any_end + mtspr 0x389,r4 + b ..ppcMtspr_any_end + mtspr 0x38a,r4 + b ..ppcMtspr_any_end + mtspr 0x38b,r4 + b ..ppcMtspr_any_end + mtspr 0x38c,r4 + b ..ppcMtspr_any_end + mtspr 0x38d,r4 + b ..ppcMtspr_any_end + mtspr 0x38e,r4 + b ..ppcMtspr_any_end + mtspr 0x38f,r4 + b ..ppcMtspr_any_end + mtspr 0x390,r4 + b ..ppcMtspr_any_end + mtspr 0x391,r4 + b ..ppcMtspr_any_end + mtspr 0x392,r4 + b ..ppcMtspr_any_end + mtspr 0x393,r4 + b ..ppcMtspr_any_end + mtspr 0x394,r4 + b ..ppcMtspr_any_end + mtspr 0x395,r4 + b ..ppcMtspr_any_end + mtspr 0x396,r4 + b ..ppcMtspr_any_end + mtspr 0x397,r4 + b ..ppcMtspr_any_end + mtspr 0x398,r4 + b ..ppcMtspr_any_end + mtspr 0x399,r4 + b ..ppcMtspr_any_end + mtspr 0x39a,r4 + b ..ppcMtspr_any_end + mtspr 0x39b,r4 + b ..ppcMtspr_any_end + mtspr 0x39c,r4 + b ..ppcMtspr_any_end + mtspr 0x39d,r4 + b ..ppcMtspr_any_end + mtspr 0x39e,r4 + b ..ppcMtspr_any_end + mtspr 0x39f,r4 + b ..ppcMtspr_any_end + mtspr 0x3a0,r4 + b ..ppcMtspr_any_end + mtspr 0x3a1,r4 + b ..ppcMtspr_any_end + mtspr 0x3a2,r4 + b ..ppcMtspr_any_end + mtspr 0x3a3,r4 + b ..ppcMtspr_any_end + mtspr 0x3a4,r4 + b ..ppcMtspr_any_end + mtspr 0x3a5,r4 + b ..ppcMtspr_any_end + mtspr 0x3a6,r4 + b ..ppcMtspr_any_end + mtspr 0x3a7,r4 + b ..ppcMtspr_any_end + mtspr 0x3a8,r4 + b ..ppcMtspr_any_end + mtspr 0x3a9,r4 + b ..ppcMtspr_any_end + mtspr 0x3aa,r4 + b ..ppcMtspr_any_end + mtspr 0x3ab,r4 + b ..ppcMtspr_any_end + mtspr 0x3ac,r4 + b ..ppcMtspr_any_end + mtspr 0x3ad,r4 + b ..ppcMtspr_any_end + mtspr 0x3ae,r4 + b ..ppcMtspr_any_end + mtspr 0x3af,r4 + b ..ppcMtspr_any_end + mtspr 0x3b0,r4 + b ..ppcMtspr_any_end + mtspr 0x3b1,r4 + b ..ppcMtspr_any_end + mtspr 0x3b2,r4 + b ..ppcMtspr_any_end + mtspr 0x3b3,r4 + b ..ppcMtspr_any_end + mtspr 0x3b4,r4 + b ..ppcMtspr_any_end + mtspr 0x3b5,r4 + b ..ppcMtspr_any_end + mtspr 0x3b6,r4 + b ..ppcMtspr_any_end + mtspr 0x3b7,r4 + b ..ppcMtspr_any_end + mtspr 0x3b8,r4 + b ..ppcMtspr_any_end + mtspr 0x3b9,r4 + b ..ppcMtspr_any_end + mtspr 0x3ba,r4 + b ..ppcMtspr_any_end + mtspr 0x3bb,r4 + b ..ppcMtspr_any_end + mtspr 0x3bc,r4 + b ..ppcMtspr_any_end + mtspr 0x3bd,r4 + b ..ppcMtspr_any_end + mtspr 0x3be,r4 + b ..ppcMtspr_any_end + mtspr 0x3bf,r4 + b ..ppcMtspr_any_end + mtspr 0x3c0,r4 + b ..ppcMtspr_any_end + mtspr 0x3c1,r4 + b ..ppcMtspr_any_end + mtspr 0x3c2,r4 + b ..ppcMtspr_any_end + mtspr 0x3c3,r4 + b ..ppcMtspr_any_end + mtspr 0x3c4,r4 + b ..ppcMtspr_any_end + mtspr 0x3c5,r4 + b ..ppcMtspr_any_end + mtspr 0x3c6,r4 + b ..ppcMtspr_any_end + mtspr 0x3c7,r4 + b ..ppcMtspr_any_end + mtspr 0x3c8,r4 + b ..ppcMtspr_any_end + mtspr 0x3c9,r4 + b ..ppcMtspr_any_end + mtspr 0x3ca,r4 + b ..ppcMtspr_any_end + mtspr 0x3cb,r4 + b ..ppcMtspr_any_end + mtspr 0x3cc,r4 + b ..ppcMtspr_any_end + mtspr 0x3cd,r4 + b ..ppcMtspr_any_end + mtspr 0x3ce,r4 + b ..ppcMtspr_any_end + mtspr 0x3cf,r4 + b ..ppcMtspr_any_end + mtspr 0x3d0,r4 + b ..ppcMtspr_any_end + mtspr 0x3d1,r4 + b ..ppcMtspr_any_end + mtspr 0x3d2,r4 + b ..ppcMtspr_any_end + mtspr 0x3d3,r4 + b ..ppcMtspr_any_end + mtspr 0x3d4,r4 + b ..ppcMtspr_any_end + mtspr 0x3d5,r4 + b ..ppcMtspr_any_end + mtspr 0x3d6,r4 + b ..ppcMtspr_any_end + mtspr 0x3d7,r4 + b ..ppcMtspr_any_end + mtspr 0x3d8,r4 + b ..ppcMtspr_any_end + mtspr 0x3d9,r4 + b ..ppcMtspr_any_end + mtspr 0x3da,r4 + b ..ppcMtspr_any_end + mtspr 0x3db,r4 + b ..ppcMtspr_any_end + mtspr 0x3dc,r4 + b ..ppcMtspr_any_end + mtspr 0x3dd,r4 + b ..ppcMtspr_any_end + mtspr 0x3de,r4 + b ..ppcMtspr_any_end + mtspr 0x3df,r4 + b ..ppcMtspr_any_end + mtspr 0x3e0,r4 + b ..ppcMtspr_any_end + mtspr 0x3e1,r4 + b ..ppcMtspr_any_end + mtspr 0x3e2,r4 + b ..ppcMtspr_any_end + mtspr 0x3e3,r4 + b ..ppcMtspr_any_end + mtspr 0x3e4,r4 + b ..ppcMtspr_any_end + mtspr 0x3e5,r4 + b ..ppcMtspr_any_end + mtspr 0x3e6,r4 + b ..ppcMtspr_any_end + mtspr 0x3e7,r4 + b ..ppcMtspr_any_end + mtspr 0x3e8,r4 + b ..ppcMtspr_any_end + mtspr 0x3e9,r4 + b ..ppcMtspr_any_end + mtspr 0x3ea,r4 + b ..ppcMtspr_any_end + mtspr 0x3eb,r4 + b ..ppcMtspr_any_end + mtspr 0x3ec,r4 + b ..ppcMtspr_any_end + mtspr 0x3ed,r4 + b ..ppcMtspr_any_end + mtspr 0x3ee,r4 + b ..ppcMtspr_any_end + mtspr 0x3ef,r4 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + mtspr 0x3f2,r4 + b ..ppcMtspr_any_end + mtspr 0x3f3,r4 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + mtspr 0x3f5,r4 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + mtspr 0x3f7,r4 + b ..ppcMtspr_any_end + mtspr 0x3f8,r4 + b ..ppcMtspr_any_end + mtspr 0x3f9,r4 + b ..ppcMtspr_any_end + mtspr 0x3fa,r4 + b ..ppcMtspr_any_end + mtspr 0x3fb,r4 + b ..ppcMtspr_any_end + mtspr 0x3fc,r4 + b ..ppcMtspr_any_end + mtspr 0x3fd,r4 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end + addi r3,r0,0x0000 + b ..ppcMtspr_any_end +..ppcMtspr_any_end: + mtlr r6 + blr + function_epilog(ppcMtspr_any) + +/*----------------------------------------------------------------------------+ +| PpcMfspr_any ++----------------------------------------------------------------------------*/ + function_prolog(ppcMfspr_any) + rlwinm r3,r3,3,19,29 + addi r3,r3,0x0010 + mflr r6 + bl ..sp_gett_lr +..sp_gett_lr: + mflr r5 + add r5,r5,r3 + mtlr r5 + blr + mfspr r3,0x000 + b ..ppcMfspr_any_end + mfspr r3,0x001 + b ..ppcMfspr_any_end + mfspr r3,0x002 + b ..ppcMfspr_any_end + mfspr r3,0x003 + b ..ppcMfspr_any_end + mfspr r3,0x004 + b ..ppcMfspr_any_end + mfspr r3,0x005 + b ..ppcMfspr_any_end + mfspr r3,0x006 + b ..ppcMfspr_any_end + mfspr r3,0x007 + b ..ppcMfspr_any_end + mfspr r3,0x008 + b ..ppcMfspr_any_end + mfspr r3,0x009 + b ..ppcMfspr_any_end + mfspr r3,0x00a + b ..ppcMfspr_any_end + mfspr r3,0x00b + b ..ppcMfspr_any_end + mfspr r3,0x00c + b ..ppcMfspr_any_end + mfspr r3,0x00d + b ..ppcMfspr_any_end + mfspr r3,0x00e + b ..ppcMfspr_any_end + mfspr r3,0x00f + b ..ppcMfspr_any_end + mfspr r3,0x010 + b ..ppcMfspr_any_end + mfspr r3,0x011 + b ..ppcMfspr_any_end + mfspr r3,0x012 + b ..ppcMfspr_any_end + mfspr r3,0x013 + b ..ppcMfspr_any_end + mfspr r3,0x014 + b ..ppcMfspr_any_end + mfspr r3,0x015 + b ..ppcMfspr_any_end + mfspr r3,0x016 + b ..ppcMfspr_any_end + mfspr r3,0x017 + b ..ppcMfspr_any_end + mfspr r3,0x018 + b ..ppcMfspr_any_end + mfspr r3,0x019 + b ..ppcMfspr_any_end + mfspr r3,0x01a + b ..ppcMfspr_any_end + mfspr r3,0x01b + b ..ppcMfspr_any_end + mfspr r3,0x01c + b ..ppcMfspr_any_end + mfspr r3,0x01d + b ..ppcMfspr_any_end + mfspr r3,0x01e + b ..ppcMfspr_any_end + mfspr r3,0x01f + b ..ppcMfspr_any_end + mfspr r3,0x020 + b ..ppcMfspr_any_end + mfspr r3,0x021 + b ..ppcMfspr_any_end + mfspr r3,0x022 + b ..ppcMfspr_any_end + mfspr r3,0x023 + b ..ppcMfspr_any_end + mfspr r3,0x024 + b ..ppcMfspr_any_end + mfspr r3,0x025 + b ..ppcMfspr_any_end + mfspr r3,0x026 + b ..ppcMfspr_any_end + mfspr r3,0x027 + b ..ppcMfspr_any_end + mfspr r3,0x028 + b ..ppcMfspr_any_end + mfspr r3,0x029 + b ..ppcMfspr_any_end + mfspr r3,0x02a + b ..ppcMfspr_any_end + mfspr r3,0x02b + b ..ppcMfspr_any_end + mfspr r3,0x02c + b ..ppcMfspr_any_end + mfspr r3,0x02d + b ..ppcMfspr_any_end + mfspr r3,0x02e + b ..ppcMfspr_any_end + mfspr r3,0x02f + b ..ppcMfspr_any_end + mfspr r3,0x030 + b ..ppcMfspr_any_end + mfspr r3,0x031 + b ..ppcMfspr_any_end + mfspr r3,0x032 + b ..ppcMfspr_any_end + mfspr r3,0x033 + b ..ppcMfspr_any_end + mfspr r3,0x034 + b ..ppcMfspr_any_end + mfspr r3,0x035 + b ..ppcMfspr_any_end + mfspr r3,0x036 + b ..ppcMfspr_any_end + mfspr r3,0x037 + b ..ppcMfspr_any_end + mfspr r3,0x038 + b ..ppcMfspr_any_end + mfspr r3,0x039 + b ..ppcMfspr_any_end + mfspr r3,0x03a + b ..ppcMfspr_any_end + mfspr r3,0x03b + b ..ppcMfspr_any_end + mfspr r3,0x03c + b ..ppcMfspr_any_end + mfspr r3,0x03d + b ..ppcMfspr_any_end + mfspr r3,0x03e + b ..ppcMfspr_any_end + mfspr r3,0x03f + b ..ppcMfspr_any_end + mfspr r3,0x040 + b ..ppcMfspr_any_end + mfspr r3,0x041 + b ..ppcMfspr_any_end + mfspr r3,0x042 + b ..ppcMfspr_any_end + mfspr r3,0x043 + b ..ppcMfspr_any_end + mfspr r3,0x044 + b ..ppcMfspr_any_end + mfspr r3,0x045 + b ..ppcMfspr_any_end + mfspr r3,0x046 + b ..ppcMfspr_any_end + mfspr r3,0x047 + b ..ppcMfspr_any_end + mfspr r3,0x048 + b ..ppcMfspr_any_end + mfspr r3,0x049 + b ..ppcMfspr_any_end + mfspr r3,0x04a + b ..ppcMfspr_any_end + mfspr r3,0x04b + b ..ppcMfspr_any_end + mfspr r3,0x04c + b ..ppcMfspr_any_end + mfspr r3,0x04d + b ..ppcMfspr_any_end + mfspr r3,0x04e + b ..ppcMfspr_any_end + mfspr r3,0x04f + b ..ppcMfspr_any_end + mfspr r3,0x050 + b ..ppcMfspr_any_end + mfspr r3,0x051 + b ..ppcMfspr_any_end + mfspr r3,0x052 + b ..ppcMfspr_any_end + mfspr r3,0x053 + b ..ppcMfspr_any_end + mfspr r3,0x054 + b ..ppcMfspr_any_end + mfspr r3,0x055 + b ..ppcMfspr_any_end + mfspr r3,0x056 + b ..ppcMfspr_any_end + mfspr r3,0x057 + b ..ppcMfspr_any_end + mfspr r3,0x058 + b ..ppcMfspr_any_end + mfspr r3,0x059 + b ..ppcMfspr_any_end + mfspr r3,0x05a + b ..ppcMfspr_any_end + mfspr r3,0x05b + b ..ppcMfspr_any_end + mfspr r3,0x05c + b ..ppcMfspr_any_end + mfspr r3,0x05d + b ..ppcMfspr_any_end + mfspr r3,0x05e + b ..ppcMfspr_any_end + mfspr r3,0x05f + b ..ppcMfspr_any_end + mfspr r3,0x060 + b ..ppcMfspr_any_end + mfspr r3,0x061 + b ..ppcMfspr_any_end + mfspr r3,0x062 + b ..ppcMfspr_any_end + mfspr r3,0x063 + b ..ppcMfspr_any_end + mfspr r3,0x064 + b ..ppcMfspr_any_end + mfspr r3,0x065 + b ..ppcMfspr_any_end + mfspr r3,0x066 + b ..ppcMfspr_any_end + mfspr r3,0x067 + b ..ppcMfspr_any_end + mfspr r3,0x068 + b ..ppcMfspr_any_end + mfspr r3,0x069 + b ..ppcMfspr_any_end + mfspr r3,0x06a + b ..ppcMfspr_any_end + mfspr r3,0x06b + b ..ppcMfspr_any_end + mfspr r3,0x06c + b ..ppcMfspr_any_end + mfspr r3,0x06d + b ..ppcMfspr_any_end + mfspr r3,0x06e + b ..ppcMfspr_any_end + mfspr r3,0x06f + b ..ppcMfspr_any_end + mfspr r3,0x070 + b ..ppcMfspr_any_end + mfspr r3,0x071 + b ..ppcMfspr_any_end + mfspr r3,0x072 + b ..ppcMfspr_any_end + mfspr r3,0x073 + b ..ppcMfspr_any_end + mfspr r3,0x074 + b ..ppcMfspr_any_end + mfspr r3,0x075 + b ..ppcMfspr_any_end + mfspr r3,0x076 + b ..ppcMfspr_any_end + mfspr r3,0x077 + b ..ppcMfspr_any_end + mfspr r3,0x078 + b ..ppcMfspr_any_end + mfspr r3,0x079 + b ..ppcMfspr_any_end + mfspr r3,0x07a + b ..ppcMfspr_any_end + mfspr r3,0x07b + b ..ppcMfspr_any_end + mfspr r3,0x07c + b ..ppcMfspr_any_end + mfspr r3,0x07d + b ..ppcMfspr_any_end + mfspr r3,0x07e + b ..ppcMfspr_any_end + mfspr r3,0x07f + b ..ppcMfspr_any_end + mfspr r3,0x080 + b ..ppcMfspr_any_end + mfspr r3,0x081 + b ..ppcMfspr_any_end + mfspr r3,0x082 + b ..ppcMfspr_any_end + mfspr r3,0x083 + b ..ppcMfspr_any_end + mfspr r3,0x084 + b ..ppcMfspr_any_end + mfspr r3,0x085 + b ..ppcMfspr_any_end + mfspr r3,0x086 + b ..ppcMfspr_any_end + mfspr r3,0x087 + b ..ppcMfspr_any_end + mfspr r3,0x088 + b ..ppcMfspr_any_end + mfspr r3,0x089 + b ..ppcMfspr_any_end + mfspr r3,0x08a + b ..ppcMfspr_any_end + mfspr r3,0x08b + b ..ppcMfspr_any_end + mfspr r3,0x08c + b ..ppcMfspr_any_end + mfspr r3,0x08d + b ..ppcMfspr_any_end + mfspr r3,0x08e + b ..ppcMfspr_any_end + mfspr r3,0x08f + b ..ppcMfspr_any_end + mfspr r3,0x090 + b ..ppcMfspr_any_end + mfspr r3,0x091 + b ..ppcMfspr_any_end + mfspr r3,0x092 + b ..ppcMfspr_any_end + mfspr r3,0x093 + b ..ppcMfspr_any_end + mfspr r3,0x094 + b ..ppcMfspr_any_end + mfspr r3,0x095 + b ..ppcMfspr_any_end + mfspr r3,0x096 + b ..ppcMfspr_any_end + mfspr r3,0x097 + b ..ppcMfspr_any_end + mfspr r3,0x098 + b ..ppcMfspr_any_end + mfspr r3,0x099 + b ..ppcMfspr_any_end + mfspr r3,0x09a + b ..ppcMfspr_any_end + mfspr r3,0x09b + b ..ppcMfspr_any_end + mfspr r3,0x09c + b ..ppcMfspr_any_end + mfspr r3,0x09d + b ..ppcMfspr_any_end + mfspr r3,0x09e + b ..ppcMfspr_any_end + mfspr r3,0x09f + b ..ppcMfspr_any_end + mfspr r3,0x0a0 + b ..ppcMfspr_any_end + mfspr r3,0x0a1 + b ..ppcMfspr_any_end + mfspr r3,0x0a2 + b ..ppcMfspr_any_end + mfspr r3,0x0a3 + b ..ppcMfspr_any_end + mfspr r3,0x0a4 + b ..ppcMfspr_any_end + mfspr r3,0x0a5 + b ..ppcMfspr_any_end + mfspr r3,0x0a6 + b ..ppcMfspr_any_end + mfspr r3,0x0a7 + b ..ppcMfspr_any_end + mfspr r3,0x0a8 + b ..ppcMfspr_any_end + mfspr r3,0x0a9 + b ..ppcMfspr_any_end + mfspr r3,0x0aa + b ..ppcMfspr_any_end + mfspr r3,0x0ab + b ..ppcMfspr_any_end + mfspr r3,0x0ac + b ..ppcMfspr_any_end + mfspr r3,0x0ad + b ..ppcMfspr_any_end + mfspr r3,0x0ae + b ..ppcMfspr_any_end + mfspr r3,0x0af + b ..ppcMfspr_any_end + mfspr r3,0x0b0 + b ..ppcMfspr_any_end + mfspr r3,0x0b1 + b ..ppcMfspr_any_end + mfspr r3,0x0b2 + b ..ppcMfspr_any_end + mfspr r3,0x0b3 + b ..ppcMfspr_any_end + mfspr r3,0x0b4 + b ..ppcMfspr_any_end + mfspr r3,0x0b5 + b ..ppcMfspr_any_end + mfspr r3,0x0b6 + b ..ppcMfspr_any_end + mfspr r3,0x0b7 + b ..ppcMfspr_any_end + mfspr r3,0x0b8 + b ..ppcMfspr_any_end + mfspr r3,0x0b9 + b ..ppcMfspr_any_end + mfspr r3,0x0ba + b ..ppcMfspr_any_end + mfspr r3,0x0bb + b ..ppcMfspr_any_end + mfspr r3,0x0bc + b ..ppcMfspr_any_end + mfspr r3,0x0bd + b ..ppcMfspr_any_end + mfspr r3,0x0be + b ..ppcMfspr_any_end + mfspr r3,0x0bf + b ..ppcMfspr_any_end + mfspr r3,0x0c0 + b ..ppcMfspr_any_end + mfspr r3,0x0c1 + b ..ppcMfspr_any_end + mfspr r3,0x0c2 + b ..ppcMfspr_any_end + mfspr r3,0x0c3 + b ..ppcMfspr_any_end + mfspr r3,0x0c4 + b ..ppcMfspr_any_end + mfspr r3,0x0c5 + b ..ppcMfspr_any_end + mfspr r3,0x0c6 + b ..ppcMfspr_any_end + mfspr r3,0x0c7 + b ..ppcMfspr_any_end + mfspr r3,0x0c8 + b ..ppcMfspr_any_end + mfspr r3,0x0c9 + b ..ppcMfspr_any_end + mfspr r3,0x0ca + b ..ppcMfspr_any_end + mfspr r3,0x0cb + b ..ppcMfspr_any_end + mfspr r3,0x0cc + b ..ppcMfspr_any_end + mfspr r3,0x0cd + b ..ppcMfspr_any_end + mfspr r3,0x0ce + b ..ppcMfspr_any_end + mfspr r3,0x0cf + b ..ppcMfspr_any_end + mfspr r3,0x0d0 + b ..ppcMfspr_any_end + mfspr r3,0x0d1 + b ..ppcMfspr_any_end + mfspr r3,0x0d2 + b ..ppcMfspr_any_end + mfspr r3,0x0d3 + b ..ppcMfspr_any_end + mfspr r3,0x0d4 + b ..ppcMfspr_any_end + mfspr r3,0x0d5 + b ..ppcMfspr_any_end + mfspr r3,0x0d6 + b ..ppcMfspr_any_end + mfspr r3,0x0d7 + b ..ppcMfspr_any_end + mfspr r3,0x0d8 + b ..ppcMfspr_any_end + mfspr r3,0x0d9 + b ..ppcMfspr_any_end + mfspr r3,0x0da + b ..ppcMfspr_any_end + mfspr r3,0x0db + b ..ppcMfspr_any_end + mfspr r3,0x0dc + b ..ppcMfspr_any_end + mfspr r3,0x0dd + b ..ppcMfspr_any_end + mfspr r3,0x0de + b ..ppcMfspr_any_end + mfspr r3,0x0df + b ..ppcMfspr_any_end + mfspr r3,0x0e0 + b ..ppcMfspr_any_end + mfspr r3,0x0e1 + b ..ppcMfspr_any_end + mfspr r3,0x0e2 + b ..ppcMfspr_any_end + mfspr r3,0x0e3 + b ..ppcMfspr_any_end + mfspr r3,0x0e4 + b ..ppcMfspr_any_end + mfspr r3,0x0e5 + b ..ppcMfspr_any_end + mfspr r3,0x0e6 + b ..ppcMfspr_any_end + mfspr r3,0x0e7 + b ..ppcMfspr_any_end + mfspr r3,0x0e8 + b ..ppcMfspr_any_end + mfspr r3,0x0e9 + b ..ppcMfspr_any_end + mfspr r3,0x0ea + b ..ppcMfspr_any_end + mfspr r3,0x0eb + b ..ppcMfspr_any_end + mfspr r3,0x0ec + b ..ppcMfspr_any_end + mfspr r3,0x0ed + b ..ppcMfspr_any_end + mfspr r3,0x0ee + b ..ppcMfspr_any_end + mfspr r3,0x0ef + b ..ppcMfspr_any_end + mfspr r3,0x0f0 + b ..ppcMfspr_any_end + mfspr r3,0x0f1 + b ..ppcMfspr_any_end + mfspr r3,0x0f2 + b ..ppcMfspr_any_end + mfspr r3,0x0f3 + b ..ppcMfspr_any_end + mfspr r3,0x0f4 + b ..ppcMfspr_any_end + mfspr r3,0x0f5 + b ..ppcMfspr_any_end + mfspr r3,0x0f6 + b ..ppcMfspr_any_end + mfspr r3,0x0f7 + b ..ppcMfspr_any_end + mfspr r3,0x0f8 + b ..ppcMfspr_any_end + mfspr r3,0x0f9 + b ..ppcMfspr_any_end + mfspr r3,0x0fa + b ..ppcMfspr_any_end + mfspr r3,0x0fb + b ..ppcMfspr_any_end + mfspr r3,0x0fc + b ..ppcMfspr_any_end + mfspr r3,0x0fd + b ..ppcMfspr_any_end + mfspr r3,0x0fe + b ..ppcMfspr_any_end + mfspr r3,0x0ff + b ..ppcMfspr_any_end + mfspr r3,0x100 + b ..ppcMfspr_any_end + mfspr r3,0x101 + b ..ppcMfspr_any_end + mfspr r3,0x102 + b ..ppcMfspr_any_end + mfspr r3,0x103 + b ..ppcMfspr_any_end + mfspr r3,0x104 + b ..ppcMfspr_any_end + mfspr r3,0x105 + b ..ppcMfspr_any_end + mfspr r3,0x106 + b ..ppcMfspr_any_end + mfspr r3,0x107 + b ..ppcMfspr_any_end + mfspr r3,0x108 + b ..ppcMfspr_any_end + mfspr r3,0x109 + b ..ppcMfspr_any_end + mfspr r3,0x10a + b ..ppcMfspr_any_end + mfspr r3,0x10b + b ..ppcMfspr_any_end + mfspr r3,0x10c + b ..ppcMfspr_any_end + mfspr r3,0x10d + b ..ppcMfspr_any_end + mfspr r3,0x10e + b ..ppcMfspr_any_end + mfspr r3,0x10f + b ..ppcMfspr_any_end + mfspr r3,0x110 + b ..ppcMfspr_any_end + mfspr r3,0x111 + b ..ppcMfspr_any_end + mfspr r3,0x112 + b ..ppcMfspr_any_end + mfspr r3,0x113 + b ..ppcMfspr_any_end + mfspr r3,0x114 + b ..ppcMfspr_any_end + mfspr r3,0x115 + b ..ppcMfspr_any_end + mfspr r3,0x116 + b ..ppcMfspr_any_end + mfspr r3,0x117 + b ..ppcMfspr_any_end + mfspr r3,0x118 + b ..ppcMfspr_any_end + mfspr r3,0x119 + b ..ppcMfspr_any_end + mfspr r3,0x11a + b ..ppcMfspr_any_end + mfspr r3,0x11b + b ..ppcMfspr_any_end + addi r3,r0,0x0000 + b ..ppcMfspr_any_end + addi r3,r0,0x0000 + b ..ppcMfspr_any_end + mfspr r3,0x11e + b ..ppcMfspr_any_end + mfspr r3,0x11f + b ..ppcMfspr_any_end + mfspr r3,0x120 + b ..ppcMfspr_any_end + mfspr r3,0x121 + b ..ppcMfspr_any_end + mfspr r3,0x122 + b ..ppcMfspr_any_end + mfspr r3,0x123 + b ..ppcMfspr_any_end + mfspr r3,0x124 + b ..ppcMfspr_any_end + mfspr r3,0x125 + b ..ppcMfspr_any_end + mfspr r3,0x126 + b ..ppcMfspr_any_end + mfspr r3,0x127 + b ..ppcMfspr_any_end + mfspr r3,0x128 + b ..ppcMfspr_any_end + mfspr r3,0x129 + b ..ppcMfspr_any_end + mfspr r3,0x12a + b ..ppcMfspr_any_end + mfspr r3,0x12b + b ..ppcMfspr_any_end + mfspr r3,0x12c + b ..ppcMfspr_any_end + mfspr r3,0x12d + b ..ppcMfspr_any_end + mfspr r3,0x12e + b ..ppcMfspr_any_end + mfspr r3,0x12f + b ..ppcMfspr_any_end + mfspr r3,0x130 + b ..ppcMfspr_any_end + mfspr r3,0x131 + b ..ppcMfspr_any_end + mfspr r3,0x132 + b ..ppcMfspr_any_end + mfspr r3,0x133 + b ..ppcMfspr_any_end + mfspr r3,0x134 + b ..ppcMfspr_any_end + mfspr r3,0x135 + b ..ppcMfspr_any_end + mfspr r3,0x136 + b ..ppcMfspr_any_end + mfspr r3,0x137 + b ..ppcMfspr_any_end + mfspr r3,0x138 + b ..ppcMfspr_any_end + mfspr r3,0x139 + b ..ppcMfspr_any_end + mfspr r3,0x13a + b ..ppcMfspr_any_end + mfspr r3,0x13b + b ..ppcMfspr_any_end + mfspr r3,0x13c + b ..ppcMfspr_any_end + mfspr r3,0x13d + b ..ppcMfspr_any_end + mfspr r3,0x13e + b ..ppcMfspr_any_end + mfspr r3,0x13f + b ..ppcMfspr_any_end + mfspr r3,0x140 + b ..ppcMfspr_any_end + mfspr r3,0x141 + b ..ppcMfspr_any_end + mfspr r3,0x142 + b ..ppcMfspr_any_end + mfspr r3,0x143 + b ..ppcMfspr_any_end + mfspr r3,0x144 + b ..ppcMfspr_any_end + mfspr r3,0x145 + b ..ppcMfspr_any_end + mfspr r3,0x146 + b ..ppcMfspr_any_end + mfspr r3,0x147 + b ..ppcMfspr_any_end + mfspr r3,0x148 + b ..ppcMfspr_any_end + mfspr r3,0x149 + b ..ppcMfspr_any_end + mfspr r3,0x14a + b ..ppcMfspr_any_end + mfspr r3,0x14b + b ..ppcMfspr_any_end + mfspr r3,0x14c + b ..ppcMfspr_any_end + mfspr r3,0x14d + b ..ppcMfspr_any_end + mfspr r3,0x14e + b ..ppcMfspr_any_end + mfspr r3,0x14f + b ..ppcMfspr_any_end + mfspr r3,0x150 + b ..ppcMfspr_any_end + mfspr r3,0x151 + b ..ppcMfspr_any_end + mfspr r3,0x152 + b ..ppcMfspr_any_end + mfspr r3,0x153 + b ..ppcMfspr_any_end + mfspr r3,0x154 + b ..ppcMfspr_any_end + mfspr r3,0x155 + b ..ppcMfspr_any_end + mfspr r3,0x156 + b ..ppcMfspr_any_end + mfspr r3,0x157 + b ..ppcMfspr_any_end + mfspr r3,0x158 + b ..ppcMfspr_any_end + mfspr r3,0x159 + b ..ppcMfspr_any_end + mfspr r3,0x15a + b ..ppcMfspr_any_end + mfspr r3,0x15b + b ..ppcMfspr_any_end + mfspr r3,0x15c + b ..ppcMfspr_any_end + mfspr r3,0x15d + b ..ppcMfspr_any_end + mfspr r3,0x15e + b ..ppcMfspr_any_end + mfspr r3,0x15f + b ..ppcMfspr_any_end + mfspr r3,0x160 + b ..ppcMfspr_any_end + mfspr r3,0x161 + b ..ppcMfspr_any_end + mfspr r3,0x162 + b ..ppcMfspr_any_end + mfspr r3,0x163 + b ..ppcMfspr_any_end + mfspr r3,0x164 + b ..ppcMfspr_any_end + mfspr r3,0x165 + b ..ppcMfspr_any_end + mfspr r3,0x166 + b ..ppcMfspr_any_end + mfspr r3,0x167 + b ..ppcMfspr_any_end + mfspr r3,0x168 + b ..ppcMfspr_any_end + mfspr r3,0x169 + b ..ppcMfspr_any_end + mfspr r3,0x16a + b ..ppcMfspr_any_end + mfspr r3,0x16b + b ..ppcMfspr_any_end + mfspr r3,0x16c + b ..ppcMfspr_any_end + mfspr r3,0x16d + b ..ppcMfspr_any_end + mfspr r3,0x16e + b ..ppcMfspr_any_end + mfspr r3,0x16f + b ..ppcMfspr_any_end + mfspr r3,0x170 + b ..ppcMfspr_any_end + mfspr r3,0x171 + b ..ppcMfspr_any_end + mfspr r3,0x172 + b ..ppcMfspr_any_end + mfspr r3,0x173 + b ..ppcMfspr_any_end + mfspr r3,0x174 + b ..ppcMfspr_any_end + mfspr r3,0x175 + b ..ppcMfspr_any_end + mfspr r3,0x176 + b ..ppcMfspr_any_end + mfspr r3,0x177 + b ..ppcMfspr_any_end + mfspr r3,0x178 + b ..ppcMfspr_any_end + mfspr r3,0x179 + b ..ppcMfspr_any_end + mfspr r3,0x17a + b ..ppcMfspr_any_end + mfspr r3,0x17b + b ..ppcMfspr_any_end + mfspr r3,0x17c + b ..ppcMfspr_any_end + mfspr r3,0x17d + b ..ppcMfspr_any_end + mfspr r3,0x17e + b ..ppcMfspr_any_end + mfspr r3,0x17f + b ..ppcMfspr_any_end + mfspr r3,0x180 + b ..ppcMfspr_any_end + mfspr r3,0x181 + b ..ppcMfspr_any_end + mfspr r3,0x182 + b ..ppcMfspr_any_end + mfspr r3,0x183 + b ..ppcMfspr_any_end + mfspr r3,0x184 + b ..ppcMfspr_any_end + mfspr r3,0x185 + b ..ppcMfspr_any_end + mfspr r3,0x186 + b ..ppcMfspr_any_end + mfspr r3,0x187 + b ..ppcMfspr_any_end + mfspr r3,0x188 + b ..ppcMfspr_any_end + mfspr r3,0x189 + b ..ppcMfspr_any_end + mfspr r3,0x18a + b ..ppcMfspr_any_end + mfspr r3,0x18b + b ..ppcMfspr_any_end + mfspr r3,0x18c + b ..ppcMfspr_any_end + mfspr r3,0x18d + b ..ppcMfspr_any_end + mfspr r3,0x18e + b ..ppcMfspr_any_end + mfspr r3,0x18f + b ..ppcMfspr_any_end + mfspr r3,0x190 + b ..ppcMfspr_any_end + mfspr r3,0x191 + b ..ppcMfspr_any_end + mfspr r3,0x192 + b ..ppcMfspr_any_end + mfspr r3,0x193 + b ..ppcMfspr_any_end + mfspr r3,0x194 + b ..ppcMfspr_any_end + mfspr r3,0x195 + b ..ppcMfspr_any_end + mfspr r3,0x196 + b ..ppcMfspr_any_end + mfspr r3,0x197 + b ..ppcMfspr_any_end + mfspr r3,0x198 + b ..ppcMfspr_any_end + mfspr r3,0x199 + b ..ppcMfspr_any_end + mfspr r3,0x19a + b ..ppcMfspr_any_end + mfspr r3,0x19b + b ..ppcMfspr_any_end + mfspr r3,0x19c + b ..ppcMfspr_any_end + mfspr r3,0x19d + b ..ppcMfspr_any_end + mfspr r3,0x19e + b ..ppcMfspr_any_end + mfspr r3,0x19f + b ..ppcMfspr_any_end + mfspr r3,0x1a0 + b ..ppcMfspr_any_end + mfspr r3,0x1a1 + b ..ppcMfspr_any_end + mfspr r3,0x1a2 + b ..ppcMfspr_any_end + mfspr r3,0x1a3 + b ..ppcMfspr_any_end + mfspr r3,0x1a4 + b ..ppcMfspr_any_end + mfspr r3,0x1a5 + b ..ppcMfspr_any_end + mfspr r3,0x1a6 + b ..ppcMfspr_any_end + mfspr r3,0x1a7 + b ..ppcMfspr_any_end + mfspr r3,0x1a8 + b ..ppcMfspr_any_end + mfspr r3,0x1a9 + b ..ppcMfspr_any_end + mfspr r3,0x1aa + b ..ppcMfspr_any_end + mfspr r3,0x1ab + b ..ppcMfspr_any_end + mfspr r3,0x1ac + b ..ppcMfspr_any_end + mfspr r3,0x1ad + b ..ppcMfspr_any_end + mfspr r3,0x1ae + b ..ppcMfspr_any_end + mfspr r3,0x1af + b ..ppcMfspr_any_end + mfspr r3,0x1b0 + b ..ppcMfspr_any_end + mfspr r3,0x1b1 + b ..ppcMfspr_any_end + mfspr r3,0x1b2 + b ..ppcMfspr_any_end + mfspr r3,0x1b3 + b ..ppcMfspr_any_end + mfspr r3,0x1b4 + b ..ppcMfspr_any_end + mfspr r3,0x1b5 + b ..ppcMfspr_any_end + mfspr r3,0x1b6 + b ..ppcMfspr_any_end + mfspr r3,0x1b7 + b ..ppcMfspr_any_end + mfspr r3,0x1b8 + b ..ppcMfspr_any_end + mfspr r3,0x1b9 + b ..ppcMfspr_any_end + mfspr r3,0x1ba + b ..ppcMfspr_any_end + mfspr r3,0x1bb + b ..ppcMfspr_any_end + mfspr r3,0x1bc + b ..ppcMfspr_any_end + mfspr r3,0x1bd + b ..ppcMfspr_any_end + mfspr r3,0x1be + b ..ppcMfspr_any_end + mfspr r3,0x1bf + b ..ppcMfspr_any_end + mfspr r3,0x1c0 + b ..ppcMfspr_any_end + mfspr r3,0x1c1 + b ..ppcMfspr_any_end + mfspr r3,0x1c2 + b ..ppcMfspr_any_end + mfspr r3,0x1c3 + b ..ppcMfspr_any_end + mfspr r3,0x1c4 + b ..ppcMfspr_any_end + mfspr r3,0x1c5 + b ..ppcMfspr_any_end + mfspr r3,0x1c6 + b ..ppcMfspr_any_end + mfspr r3,0x1c7 + b ..ppcMfspr_any_end + mfspr r3,0x1c8 + b ..ppcMfspr_any_end + mfspr r3,0x1c9 + b ..ppcMfspr_any_end + mfspr r3,0x1ca + b ..ppcMfspr_any_end + mfspr r3,0x1cb + b ..ppcMfspr_any_end + mfspr r3,0x1cc + b ..ppcMfspr_any_end + mfspr r3,0x1cd + b ..ppcMfspr_any_end + mfspr r3,0x1ce + b ..ppcMfspr_any_end + mfspr r3,0x1cf + b ..ppcMfspr_any_end + mfspr r3,0x1d0 + b ..ppcMfspr_any_end + mfspr r3,0x1d1 + b ..ppcMfspr_any_end + mfspr r3,0x1d2 + b ..ppcMfspr_any_end + mfspr r3,0x1d3 + b ..ppcMfspr_any_end + mfspr r3,0x1d4 + b ..ppcMfspr_any_end + mfspr r3,0x1d5 + b ..ppcMfspr_any_end + mfspr r3,0x1d6 + b ..ppcMfspr_any_end + mfspr r3,0x1d7 + b ..ppcMfspr_any_end + mfspr r3,0x1d8 + b ..ppcMfspr_any_end + mfspr r3,0x1d9 + b ..ppcMfspr_any_end + mfspr r3,0x1da + b ..ppcMfspr_any_end + mfspr r3,0x1db + b ..ppcMfspr_any_end + mfspr r3,0x1dc + b ..ppcMfspr_any_end + mfspr r3,0x1dd + b ..ppcMfspr_any_end + mfspr r3,0x1de + b ..ppcMfspr_any_end + mfspr r3,0x1df + b ..ppcMfspr_any_end + mfspr r3,0x1e0 + b ..ppcMfspr_any_end + mfspr r3,0x1e1 + b ..ppcMfspr_any_end + mfspr r3,0x1e2 + b ..ppcMfspr_any_end + mfspr r3,0x1e3 + b ..ppcMfspr_any_end + mfspr r3,0x1e4 + b ..ppcMfspr_any_end + mfspr r3,0x1e5 + b ..ppcMfspr_any_end + mfspr r3,0x1e6 + b ..ppcMfspr_any_end + mfspr r3,0x1e7 + b ..ppcMfspr_any_end + mfspr r3,0x1e8 + b ..ppcMfspr_any_end + mfspr r3,0x1e9 + b ..ppcMfspr_any_end + mfspr r3,0x1ea + b ..ppcMfspr_any_end + mfspr r3,0x1eb + b ..ppcMfspr_any_end + mfspr r3,0x1ec + b ..ppcMfspr_any_end + mfspr r3,0x1ed + b ..ppcMfspr_any_end + mfspr r3,0x1ee + b ..ppcMfspr_any_end + mfspr r3,0x1ef + b ..ppcMfspr_any_end + mfspr r3,0x1f0 + b ..ppcMfspr_any_end + mfspr r3,0x1f1 + b ..ppcMfspr_any_end + mfspr r3,0x1f2 + b ..ppcMfspr_any_end + mfspr r3,0x1f3 + b ..ppcMfspr_any_end + mfspr r3,0x1f4 + b ..ppcMfspr_any_end + mfspr r3,0x1f5 + b ..ppcMfspr_any_end + mfspr r3,0x1f6 + b ..ppcMfspr_any_end + mfspr r3,0x1f7 + b ..ppcMfspr_any_end + mfspr r3,0x1f8 + b ..ppcMfspr_any_end + mfspr r3,0x1f9 + b ..ppcMfspr_any_end + mfspr r3,0x1fa + b ..ppcMfspr_any_end + mfspr r3,0x1fb + b ..ppcMfspr_any_end + mfspr r3,0x1fc + b ..ppcMfspr_any_end + mfspr r3,0x1fd + b ..ppcMfspr_any_end + mfspr r3,0x1fe + b ..ppcMfspr_any_end + mfspr r3,0x1ff + b ..ppcMfspr_any_end + mfspr r3,0x200 + b ..ppcMfspr_any_end + mfspr r3,0x201 + b ..ppcMfspr_any_end + mfspr r3,0x202 + b ..ppcMfspr_any_end + mfspr r3,0x203 + b ..ppcMfspr_any_end + mfspr r3,0x204 + b ..ppcMfspr_any_end + mfspr r3,0x205 + b ..ppcMfspr_any_end + mfspr r3,0x206 + b ..ppcMfspr_any_end + mfspr r3,0x207 + b ..ppcMfspr_any_end + mfspr r3,0x208 + b ..ppcMfspr_any_end + mfspr r3,0x209 + b ..ppcMfspr_any_end + mfspr r3,0x20a + b ..ppcMfspr_any_end + mfspr r3,0x20b + b ..ppcMfspr_any_end + mfspr r3,0x20c + b ..ppcMfspr_any_end + mfspr r3,0x20d + b ..ppcMfspr_any_end + mfspr r3,0x20e + b ..ppcMfspr_any_end + mfspr r3,0x20f + b ..ppcMfspr_any_end + mfspr r3,0x210 + b ..ppcMfspr_any_end + mfspr r3,0x211 + b ..ppcMfspr_any_end + mfspr r3,0x212 + b ..ppcMfspr_any_end + mfspr r3,0x213 + b ..ppcMfspr_any_end + mfspr r3,0x214 + b ..ppcMfspr_any_end + mfspr r3,0x215 + b ..ppcMfspr_any_end + mfspr r3,0x216 + b ..ppcMfspr_any_end + mfspr r3,0x217 + b ..ppcMfspr_any_end + mfspr r3,0x218 + b ..ppcMfspr_any_end + mfspr r3,0x219 + b ..ppcMfspr_any_end + mfspr r3,0x21a + b ..ppcMfspr_any_end + mfspr r3,0x21b + b ..ppcMfspr_any_end + mfspr r3,0x21c + b ..ppcMfspr_any_end + mfspr r3,0x21d + b ..ppcMfspr_any_end + mfspr r3,0x21e + b ..ppcMfspr_any_end + mfspr r3,0x21f + b ..ppcMfspr_any_end + mfspr r3,0x220 + b ..ppcMfspr_any_end + mfspr r3,0x221 + b ..ppcMfspr_any_end + mfspr r3,0x222 + b ..ppcMfspr_any_end + mfspr r3,0x223 + b ..ppcMfspr_any_end + mfspr r3,0x224 + b ..ppcMfspr_any_end + mfspr r3,0x225 + b ..ppcMfspr_any_end + mfspr r3,0x226 + b ..ppcMfspr_any_end + mfspr r3,0x227 + b ..ppcMfspr_any_end + mfspr r3,0x228 + b ..ppcMfspr_any_end + mfspr r3,0x229 + b ..ppcMfspr_any_end + mfspr r3,0x22a + b ..ppcMfspr_any_end + mfspr r3,0x22b + b ..ppcMfspr_any_end + mfspr r3,0x22c + b ..ppcMfspr_any_end + mfspr r3,0x22d + b ..ppcMfspr_any_end + mfspr r3,0x22e + b ..ppcMfspr_any_end + mfspr r3,0x22f + b ..ppcMfspr_any_end + mfspr r3,0x230 + b ..ppcMfspr_any_end + mfspr r3,0x231 + b ..ppcMfspr_any_end + mfspr r3,0x232 + b ..ppcMfspr_any_end + mfspr r3,0x233 + b ..ppcMfspr_any_end + mfspr r3,0x234 + b ..ppcMfspr_any_end + mfspr r3,0x235 + b ..ppcMfspr_any_end + mfspr r3,0x236 + b ..ppcMfspr_any_end + mfspr r3,0x237 + b ..ppcMfspr_any_end + mfspr r3,0x238 + b ..ppcMfspr_any_end + mfspr r3,0x239 + b ..ppcMfspr_any_end + mfspr r3,0x23a + b ..ppcMfspr_any_end + mfspr r3,0x23b + b ..ppcMfspr_any_end + mfspr r3,0x23c + b ..ppcMfspr_any_end + mfspr r3,0x23d + b ..ppcMfspr_any_end + mfspr r3,0x23e + b ..ppcMfspr_any_end + mfspr r3,0x23f + b ..ppcMfspr_any_end + mfspr r3,0x240 + b ..ppcMfspr_any_end + mfspr r3,0x241 + b ..ppcMfspr_any_end + mfspr r3,0x242 + b ..ppcMfspr_any_end + mfspr r3,0x243 + b ..ppcMfspr_any_end + mfspr r3,0x244 + b ..ppcMfspr_any_end + mfspr r3,0x245 + b ..ppcMfspr_any_end + mfspr r3,0x246 + b ..ppcMfspr_any_end + mfspr r3,0x247 + b ..ppcMfspr_any_end + mfspr r3,0x248 + b ..ppcMfspr_any_end + mfspr r3,0x249 + b ..ppcMfspr_any_end + mfspr r3,0x24a + b ..ppcMfspr_any_end + mfspr r3,0x24b + b ..ppcMfspr_any_end + mfspr r3,0x24c + b ..ppcMfspr_any_end + mfspr r3,0x24d + b ..ppcMfspr_any_end + mfspr r3,0x24e + b ..ppcMfspr_any_end + mfspr r3,0x24f + b ..ppcMfspr_any_end + mfspr r3,0x250 + b ..ppcMfspr_any_end + mfspr r3,0x251 + b ..ppcMfspr_any_end + mfspr r3,0x252 + b ..ppcMfspr_any_end + mfspr r3,0x253 + b ..ppcMfspr_any_end + mfspr r3,0x254 + b ..ppcMfspr_any_end + mfspr r3,0x255 + b ..ppcMfspr_any_end + mfspr r3,0x256 + b ..ppcMfspr_any_end + mfspr r3,0x257 + b ..ppcMfspr_any_end + mfspr r3,0x258 + b ..ppcMfspr_any_end + mfspr r3,0x259 + b ..ppcMfspr_any_end + mfspr r3,0x25a + b ..ppcMfspr_any_end + mfspr r3,0x25b + b ..ppcMfspr_any_end + mfspr r3,0x25c + b ..ppcMfspr_any_end + mfspr r3,0x25d + b ..ppcMfspr_any_end + mfspr r3,0x25e + b ..ppcMfspr_any_end + mfspr r3,0x25f + b ..ppcMfspr_any_end + mfspr r3,0x260 + b ..ppcMfspr_any_end + mfspr r3,0x261 + b ..ppcMfspr_any_end + mfspr r3,0x262 + b ..ppcMfspr_any_end + mfspr r3,0x263 + b ..ppcMfspr_any_end + mfspr r3,0x264 + b ..ppcMfspr_any_end + mfspr r3,0x265 + b ..ppcMfspr_any_end + mfspr r3,0x266 + b ..ppcMfspr_any_end + mfspr r3,0x267 + b ..ppcMfspr_any_end + mfspr r3,0x268 + b ..ppcMfspr_any_end + mfspr r3,0x269 + b ..ppcMfspr_any_end + mfspr r3,0x26a + b ..ppcMfspr_any_end + mfspr r3,0x26b + b ..ppcMfspr_any_end + mfspr r3,0x26c + b ..ppcMfspr_any_end + mfspr r3,0x26d + b ..ppcMfspr_any_end + mfspr r3,0x26e + b ..ppcMfspr_any_end + mfspr r3,0x26f + b ..ppcMfspr_any_end + mfspr r3,0x270 + b ..ppcMfspr_any_end + mfspr r3,0x271 + b ..ppcMfspr_any_end + mfspr r3,0x272 + b ..ppcMfspr_any_end + mfspr r3,0x273 + b ..ppcMfspr_any_end + mfspr r3,0x274 + b ..ppcMfspr_any_end + mfspr r3,0x275 + b ..ppcMfspr_any_end + mfspr r3,0x276 + b ..ppcMfspr_any_end + mfspr r3,0x277 + b ..ppcMfspr_any_end + mfspr r3,0x278 + b ..ppcMfspr_any_end + mfspr r3,0x279 + b ..ppcMfspr_any_end + mfspr r3,0x27a + b ..ppcMfspr_any_end + mfspr r3,0x27b + b ..ppcMfspr_any_end + mfspr r3,0x27c + b ..ppcMfspr_any_end + mfspr r3,0x27d + b ..ppcMfspr_any_end + mfspr r3,0x27e + b ..ppcMfspr_any_end + mfspr r3,0x27f + b ..ppcMfspr_any_end + mfspr r3,0x280 + b ..ppcMfspr_any_end + mfspr r3,0x281 + b ..ppcMfspr_any_end + mfspr r3,0x282 + b ..ppcMfspr_any_end + mfspr r3,0x283 + b ..ppcMfspr_any_end + mfspr r3,0x284 + b ..ppcMfspr_any_end + mfspr r3,0x285 + b ..ppcMfspr_any_end + mfspr r3,0x286 + b ..ppcMfspr_any_end + mfspr r3,0x287 + b ..ppcMfspr_any_end + mfspr r3,0x288 + b ..ppcMfspr_any_end + mfspr r3,0x289 + b ..ppcMfspr_any_end + mfspr r3,0x28a + b ..ppcMfspr_any_end + mfspr r3,0x28b + b ..ppcMfspr_any_end + mfspr r3,0x28c + b ..ppcMfspr_any_end + mfspr r3,0x28d + b ..ppcMfspr_any_end + mfspr r3,0x28e + b ..ppcMfspr_any_end + mfspr r3,0x28f + b ..ppcMfspr_any_end + mfspr r3,0x290 + b ..ppcMfspr_any_end + mfspr r3,0x291 + b ..ppcMfspr_any_end + mfspr r3,0x292 + b ..ppcMfspr_any_end + mfspr r3,0x293 + b ..ppcMfspr_any_end + mfspr r3,0x294 + b ..ppcMfspr_any_end + mfspr r3,0x295 + b ..ppcMfspr_any_end + mfspr r3,0x296 + b ..ppcMfspr_any_end + mfspr r3,0x297 + b ..ppcMfspr_any_end + mfspr r3,0x298 + b ..ppcMfspr_any_end + mfspr r3,0x299 + b ..ppcMfspr_any_end + mfspr r3,0x29a + b ..ppcMfspr_any_end + mfspr r3,0x29b + b ..ppcMfspr_any_end + mfspr r3,0x29c + b ..ppcMfspr_any_end + mfspr r3,0x29d + b ..ppcMfspr_any_end + mfspr r3,0x29e + b ..ppcMfspr_any_end + mfspr r3,0x29f + b ..ppcMfspr_any_end + mfspr r3,0x2a0 + b ..ppcMfspr_any_end + mfspr r3,0x2a1 + b ..ppcMfspr_any_end + mfspr r3,0x2a2 + b ..ppcMfspr_any_end + mfspr r3,0x2a3 + b ..ppcMfspr_any_end + mfspr r3,0x2a4 + b ..ppcMfspr_any_end + mfspr r3,0x2a5 + b ..ppcMfspr_any_end + mfspr r3,0x2a6 + b ..ppcMfspr_any_end + mfspr r3,0x2a7 + b ..ppcMfspr_any_end + mfspr r3,0x2a8 + b ..ppcMfspr_any_end + mfspr r3,0x2a9 + b ..ppcMfspr_any_end + mfspr r3,0x2aa + b ..ppcMfspr_any_end + mfspr r3,0x2ab + b ..ppcMfspr_any_end + mfspr r3,0x2ac + b ..ppcMfspr_any_end + mfspr r3,0x2ad + b ..ppcMfspr_any_end + mfspr r3,0x2ae + b ..ppcMfspr_any_end + mfspr r3,0x2af + b ..ppcMfspr_any_end + mfspr r3,0x2b0 + b ..ppcMfspr_any_end + mfspr r3,0x2b1 + b ..ppcMfspr_any_end + mfspr r3,0x2b2 + b ..ppcMfspr_any_end + mfspr r3,0x2b3 + b ..ppcMfspr_any_end + mfspr r3,0x2b4 + b ..ppcMfspr_any_end + mfspr r3,0x2b5 + b ..ppcMfspr_any_end + mfspr r3,0x2b6 + b ..ppcMfspr_any_end + mfspr r3,0x2b7 + b ..ppcMfspr_any_end + mfspr r3,0x2b8 + b ..ppcMfspr_any_end + mfspr r3,0x2b9 + b ..ppcMfspr_any_end + mfspr r3,0x2ba + b ..ppcMfspr_any_end + mfspr r3,0x2bb + b ..ppcMfspr_any_end + mfspr r3,0x2bc + b ..ppcMfspr_any_end + mfspr r3,0x2bd + b ..ppcMfspr_any_end + mfspr r3,0x2be + b ..ppcMfspr_any_end + mfspr r3,0x2bf + b ..ppcMfspr_any_end + mfspr r3,0x2c0 + b ..ppcMfspr_any_end + mfspr r3,0x2c1 + b ..ppcMfspr_any_end + mfspr r3,0x2c2 + b ..ppcMfspr_any_end + mfspr r3,0x2c3 + b ..ppcMfspr_any_end + mfspr r3,0x2c4 + b ..ppcMfspr_any_end + mfspr r3,0x2c5 + b ..ppcMfspr_any_end + mfspr r3,0x2c6 + b ..ppcMfspr_any_end + mfspr r3,0x2c7 + b ..ppcMfspr_any_end + mfspr r3,0x2c8 + b ..ppcMfspr_any_end + mfspr r3,0x2c9 + b ..ppcMfspr_any_end + mfspr r3,0x2ca + b ..ppcMfspr_any_end + mfspr r3,0x2cb + b ..ppcMfspr_any_end + mfspr r3,0x2cc + b ..ppcMfspr_any_end + mfspr r3,0x2cd + b ..ppcMfspr_any_end + mfspr r3,0x2ce + b ..ppcMfspr_any_end + mfspr r3,0x2cf + b ..ppcMfspr_any_end + mfspr r3,0x2d0 + b ..ppcMfspr_any_end + mfspr r3,0x2d1 + b ..ppcMfspr_any_end + mfspr r3,0x2d2 + b ..ppcMfspr_any_end + mfspr r3,0x2d3 + b ..ppcMfspr_any_end + mfspr r3,0x2d4 + b ..ppcMfspr_any_end + mfspr r3,0x2d5 + b ..ppcMfspr_any_end + mfspr r3,0x2d6 + b ..ppcMfspr_any_end + mfspr r3,0x2d7 + b ..ppcMfspr_any_end + mfspr r3,0x2d8 + b ..ppcMfspr_any_end + mfspr r3,0x2d9 + b ..ppcMfspr_any_end + mfspr r3,0x2da + b ..ppcMfspr_any_end + mfspr r3,0x2db + b ..ppcMfspr_any_end + mfspr r3,0x2dc + b ..ppcMfspr_any_end + mfspr r3,0x2dd + b ..ppcMfspr_any_end + mfspr r3,0x2de + b ..ppcMfspr_any_end + mfspr r3,0x2df + b ..ppcMfspr_any_end + mfspr r3,0x2e0 + b ..ppcMfspr_any_end + mfspr r3,0x2e1 + b ..ppcMfspr_any_end + mfspr r3,0x2e2 + b ..ppcMfspr_any_end + mfspr r3,0x2e3 + b ..ppcMfspr_any_end + mfspr r3,0x2e4 + b ..ppcMfspr_any_end + mfspr r3,0x2e5 + b ..ppcMfspr_any_end + mfspr r3,0x2e6 + b ..ppcMfspr_any_end + mfspr r3,0x2e7 + b ..ppcMfspr_any_end + mfspr r3,0x2e8 + b ..ppcMfspr_any_end + mfspr r3,0x2e9 + b ..ppcMfspr_any_end + mfspr r3,0x2ea + b ..ppcMfspr_any_end + mfspr r3,0x2eb + b ..ppcMfspr_any_end + mfspr r3,0x2ec + b ..ppcMfspr_any_end + mfspr r3,0x2ed + b ..ppcMfspr_any_end + mfspr r3,0x2ee + b ..ppcMfspr_any_end + mfspr r3,0x2ef + b ..ppcMfspr_any_end + mfspr r3,0x2f0 + b ..ppcMfspr_any_end + mfspr r3,0x2f1 + b ..ppcMfspr_any_end + mfspr r3,0x2f2 + b ..ppcMfspr_any_end + mfspr r3,0x2f3 + b ..ppcMfspr_any_end + mfspr r3,0x2f4 + b ..ppcMfspr_any_end + mfspr r3,0x2f5 + b ..ppcMfspr_any_end + mfspr r3,0x2f6 + b ..ppcMfspr_any_end + mfspr r3,0x2f7 + b ..ppcMfspr_any_end + mfspr r3,0x2f8 + b ..ppcMfspr_any_end + mfspr r3,0x2f9 + b ..ppcMfspr_any_end + mfspr r3,0x2fa + b ..ppcMfspr_any_end + mfspr r3,0x2fb + b ..ppcMfspr_any_end + mfspr r3,0x2fc + b ..ppcMfspr_any_end + mfspr r3,0x2fd + b ..ppcMfspr_any_end + mfspr r3,0x2fe + b ..ppcMfspr_any_end + mfspr r3,0x2ff + b ..ppcMfspr_any_end + mfspr r3,0x300 + b ..ppcMfspr_any_end + mfspr r3,0x301 + b ..ppcMfspr_any_end + mfspr r3,0x302 + b ..ppcMfspr_any_end + mfspr r3,0x303 + b ..ppcMfspr_any_end + mfspr r3,0x304 + b ..ppcMfspr_any_end + mfspr r3,0x305 + b ..ppcMfspr_any_end + mfspr r3,0x306 + b ..ppcMfspr_any_end + mfspr r3,0x307 + b ..ppcMfspr_any_end + mfspr r3,0x308 + b ..ppcMfspr_any_end + mfspr r3,0x309 + b ..ppcMfspr_any_end + mfspr r3,0x30a + b ..ppcMfspr_any_end + mfspr r3,0x30b + b ..ppcMfspr_any_end + mfspr r3,0x30c + b ..ppcMfspr_any_end + mfspr r3,0x30d + b ..ppcMfspr_any_end + mfspr r3,0x30e + b ..ppcMfspr_any_end + mfspr r3,0x30f + b ..ppcMfspr_any_end + mfspr r3,0x310 + b ..ppcMfspr_any_end + mfspr r3,0x311 + b ..ppcMfspr_any_end + mfspr r3,0x312 + b ..ppcMfspr_any_end + mfspr r3,0x313 + b ..ppcMfspr_any_end + mfspr r3,0x314 + b ..ppcMfspr_any_end + mfspr r3,0x315 + b ..ppcMfspr_any_end + mfspr r3,0x316 + b ..ppcMfspr_any_end + mfspr r3,0x317 + b ..ppcMfspr_any_end + mfspr r3,0x318 + b ..ppcMfspr_any_end + mfspr r3,0x319 + b ..ppcMfspr_any_end + mfspr r3,0x31a + b ..ppcMfspr_any_end + mfspr r3,0x31b + b ..ppcMfspr_any_end + mfspr r3,0x31c + b ..ppcMfspr_any_end + mfspr r3,0x31d + b ..ppcMfspr_any_end + mfspr r3,0x31e + b ..ppcMfspr_any_end + mfspr r3,0x31f + b ..ppcMfspr_any_end + mfspr r3,0x320 + b ..ppcMfspr_any_end + mfspr r3,0x321 + b ..ppcMfspr_any_end + mfspr r3,0x322 + b ..ppcMfspr_any_end + mfspr r3,0x323 + b ..ppcMfspr_any_end + mfspr r3,0x324 + b ..ppcMfspr_any_end + mfspr r3,0x325 + b ..ppcMfspr_any_end + mfspr r3,0x326 + b ..ppcMfspr_any_end + mfspr r3,0x327 + b ..ppcMfspr_any_end + mfspr r3,0x328 + b ..ppcMfspr_any_end + mfspr r3,0x329 + b ..ppcMfspr_any_end + mfspr r3,0x32a + b ..ppcMfspr_any_end + mfspr r3,0x32b + b ..ppcMfspr_any_end + mfspr r3,0x32c + b ..ppcMfspr_any_end + mfspr r3,0x32d + b ..ppcMfspr_any_end + mfspr r3,0x32e + b ..ppcMfspr_any_end + mfspr r3,0x32f + b ..ppcMfspr_any_end + mfspr r3,0x330 + b ..ppcMfspr_any_end + mfspr r3,0x331 + b ..ppcMfspr_any_end + mfspr r3,0x332 + b ..ppcMfspr_any_end + mfspr r3,0x333 + b ..ppcMfspr_any_end + mfspr r3,0x334 + b ..ppcMfspr_any_end + mfspr r3,0x335 + b ..ppcMfspr_any_end + mfspr r3,0x336 + b ..ppcMfspr_any_end + mfspr r3,0x337 + b ..ppcMfspr_any_end + mfspr r3,0x338 + b ..ppcMfspr_any_end + mfspr r3,0x339 + b ..ppcMfspr_any_end + mfspr r3,0x33a + b ..ppcMfspr_any_end + mfspr r3,0x33b + b ..ppcMfspr_any_end + mfspr r3,0x33c + b ..ppcMfspr_any_end + mfspr r3,0x33d + b ..ppcMfspr_any_end + mfspr r3,0x33e + b ..ppcMfspr_any_end + mfspr r3,0x33f + b ..ppcMfspr_any_end + mfspr r3,0x340 + b ..ppcMfspr_any_end + mfspr r3,0x341 + b ..ppcMfspr_any_end + mfspr r3,0x342 + b ..ppcMfspr_any_end + mfspr r3,0x343 + b ..ppcMfspr_any_end + mfspr r3,0x344 + b ..ppcMfspr_any_end + mfspr r3,0x345 + b ..ppcMfspr_any_end + mfspr r3,0x346 + b ..ppcMfspr_any_end + mfspr r3,0x347 + b ..ppcMfspr_any_end + mfspr r3,0x348 + b ..ppcMfspr_any_end + mfspr r3,0x349 + b ..ppcMfspr_any_end + mfspr r3,0x34a + b ..ppcMfspr_any_end + mfspr r3,0x34b + b ..ppcMfspr_any_end + mfspr r3,0x34c + b ..ppcMfspr_any_end + mfspr r3,0x34d + b ..ppcMfspr_any_end + mfspr r3,0x34e + b ..ppcMfspr_any_end + mfspr r3,0x34f + b ..ppcMfspr_any_end + mfspr r3,0x350 + b ..ppcMfspr_any_end + mfspr r3,0x351 + b ..ppcMfspr_any_end + mfspr r3,0x352 + b ..ppcMfspr_any_end + mfspr r3,0x353 + b ..ppcMfspr_any_end + mfspr r3,0x354 + b ..ppcMfspr_any_end + mfspr r3,0x355 + b ..ppcMfspr_any_end + mfspr r3,0x356 + b ..ppcMfspr_any_end + mfspr r3,0x357 + b ..ppcMfspr_any_end + mfspr r3,0x358 + b ..ppcMfspr_any_end + mfspr r3,0x359 + b ..ppcMfspr_any_end + mfspr r3,0x35a + b ..ppcMfspr_any_end + mfspr r3,0x35b + b ..ppcMfspr_any_end + mfspr r3,0x35c + b ..ppcMfspr_any_end + mfspr r3,0x35d + b ..ppcMfspr_any_end + mfspr r3,0x35e + b ..ppcMfspr_any_end + mfspr r3,0x35f + b ..ppcMfspr_any_end + mfspr r3,0x360 + b ..ppcMfspr_any_end + mfspr r3,0x361 + b ..ppcMfspr_any_end + mfspr r3,0x362 + b ..ppcMfspr_any_end + mfspr r3,0x363 + b ..ppcMfspr_any_end + mfspr r3,0x364 + b ..ppcMfspr_any_end + mfspr r3,0x365 + b ..ppcMfspr_any_end + mfspr r3,0x366 + b ..ppcMfspr_any_end + mfspr r3,0x367 + b ..ppcMfspr_any_end + mfspr r3,0x368 + b ..ppcMfspr_any_end + mfspr r3,0x369 + b ..ppcMfspr_any_end + mfspr r3,0x36a + b ..ppcMfspr_any_end + mfspr r3,0x36b + b ..ppcMfspr_any_end + mfspr r3,0x36c + b ..ppcMfspr_any_end + mfspr r3,0x36d + b ..ppcMfspr_any_end + mfspr r3,0x36e + b ..ppcMfspr_any_end + mfspr r3,0x36f + b ..ppcMfspr_any_end + mfspr r3,0x370 + b ..ppcMfspr_any_end + mfspr r3,0x371 + b ..ppcMfspr_any_end + mfspr r3,0x372 + b ..ppcMfspr_any_end + mfspr r3,0x373 + b ..ppcMfspr_any_end + mfspr r3,0x374 + b ..ppcMfspr_any_end + mfspr r3,0x375 + b ..ppcMfspr_any_end + mfspr r3,0x376 + b ..ppcMfspr_any_end + mfspr r3,0x377 + b ..ppcMfspr_any_end + mfspr r3,0x378 + b ..ppcMfspr_any_end + mfspr r3,0x379 + b ..ppcMfspr_any_end + mfspr r3,0x37a + b ..ppcMfspr_any_end + mfspr r3,0x37b + b ..ppcMfspr_any_end + mfspr r3,0x37c + b ..ppcMfspr_any_end + mfspr r3,0x37d + b ..ppcMfspr_any_end + mfspr r3,0x37e + b ..ppcMfspr_any_end + mfspr r3,0x37f + b ..ppcMfspr_any_end + mfspr r3,0x380 + b ..ppcMfspr_any_end + mfspr r3,0x381 + b ..ppcMfspr_any_end + mfspr r3,0x382 + b ..ppcMfspr_any_end + mfspr r3,0x383 + b ..ppcMfspr_any_end + mfspr r3,0x384 + b ..ppcMfspr_any_end + mfspr r3,0x385 + b ..ppcMfspr_any_end + mfspr r3,0x386 + b ..ppcMfspr_any_end + mfspr r3,0x387 + b ..ppcMfspr_any_end + mfspr r3,0x388 + b ..ppcMfspr_any_end + mfspr r3,0x389 + b ..ppcMfspr_any_end + mfspr r3,0x38a + b ..ppcMfspr_any_end + mfspr r3,0x38b + b ..ppcMfspr_any_end + mfspr r3,0x38c + b ..ppcMfspr_any_end + mfspr r3,0x38d + b ..ppcMfspr_any_end + mfspr r3,0x38e + b ..ppcMfspr_any_end + mfspr r3,0x38f + b ..ppcMfspr_any_end + mfspr r3,0x390 + b ..ppcMfspr_any_end + mfspr r3,0x391 + b ..ppcMfspr_any_end + mfspr r3,0x392 + b ..ppcMfspr_any_end + mfspr r3,0x393 + b ..ppcMfspr_any_end + mfspr r3,0x394 + b ..ppcMfspr_any_end + mfspr r3,0x395 + b ..ppcMfspr_any_end + mfspr r3,0x396 + b ..ppcMfspr_any_end + mfspr r3,0x397 + b ..ppcMfspr_any_end + mfspr r3,0x398 + b ..ppcMfspr_any_end + mfspr r3,0x399 + b ..ppcMfspr_any_end + mfspr r3,0x39a + b ..ppcMfspr_any_end + mfspr r3,0x39b + b ..ppcMfspr_any_end + mfspr r3,0x39c + b ..ppcMfspr_any_end + mfspr r3,0x39d + b ..ppcMfspr_any_end + mfspr r3,0x39e + b ..ppcMfspr_any_end + mfspr r3,0x39f + b ..ppcMfspr_any_end + mfspr r3,0x3a0 + b ..ppcMfspr_any_end + mfspr r3,0x3a1 + b ..ppcMfspr_any_end + mfspr r3,0x3a2 + b ..ppcMfspr_any_end + mfspr r3,0x3a3 + b ..ppcMfspr_any_end + mfspr r3,0x3a4 + b ..ppcMfspr_any_end + mfspr r3,0x3a5 + b ..ppcMfspr_any_end + mfspr r3,0x3a6 + b ..ppcMfspr_any_end + mfspr r3,0x3a7 + b ..ppcMfspr_any_end + mfspr r3,0x3a8 + b ..ppcMfspr_any_end + mfspr r3,0x3a9 + b ..ppcMfspr_any_end + mfspr r3,0x3aa + b ..ppcMfspr_any_end + mfspr r3,0x3ab + b ..ppcMfspr_any_end + mfspr r3,0x3ac + b ..ppcMfspr_any_end + mfspr r3,0x3ad + b ..ppcMfspr_any_end + mfspr r3,0x3ae + b ..ppcMfspr_any_end + mfspr r3,0x3af + b ..ppcMfspr_any_end + mfspr r3,0x3b0 + b ..ppcMfspr_any_end + mfspr r3,0x3b1 + b ..ppcMfspr_any_end + mfspr r3,0x3b2 + b ..ppcMfspr_any_end + mfspr r3,0x3b3 + b ..ppcMfspr_any_end + mfspr r3,0x3b4 + b ..ppcMfspr_any_end + mfspr r3,0x3b5 + b ..ppcMfspr_any_end + mfspr r3,0x3b6 + b ..ppcMfspr_any_end + mfspr r3,0x3b7 + b ..ppcMfspr_any_end + mfspr r3,0x3b8 + b ..ppcMfspr_any_end + mfspr r3,0x3b9 + b ..ppcMfspr_any_end + mfspr r3,0x3ba + b ..ppcMfspr_any_end + mfspr r3,0x3bb + b ..ppcMfspr_any_end + mfspr r3,0x3bc + b ..ppcMfspr_any_end + mfspr r3,0x3bd + b ..ppcMfspr_any_end + mfspr r3,0x3be + b ..ppcMfspr_any_end + mfspr r3,0x3bf + b ..ppcMfspr_any_end + mfspr r3,0x3c0 + b ..ppcMfspr_any_end + mfspr r3,0x3c1 + b ..ppcMfspr_any_end + mfspr r3,0x3c2 + b ..ppcMfspr_any_end + mfspr r3,0x3c3 + b ..ppcMfspr_any_end + mfspr r3,0x3c4 + b ..ppcMfspr_any_end + mfspr r3,0x3c5 + b ..ppcMfspr_any_end + mfspr r3,0x3c6 + b ..ppcMfspr_any_end + mfspr r3,0x3c7 + b ..ppcMfspr_any_end + mfspr r3,0x3c8 + b ..ppcMfspr_any_end + mfspr r3,0x3c9 + b ..ppcMfspr_any_end + mfspr r3,0x3ca + b ..ppcMfspr_any_end + mfspr r3,0x3cb + b ..ppcMfspr_any_end + mfspr r3,0x3cc + b ..ppcMfspr_any_end + mfspr r3,0x3cd + b ..ppcMfspr_any_end + mfspr r3,0x3ce + b ..ppcMfspr_any_end + mfspr r3,0x3cf + b ..ppcMfspr_any_end + addi r3,r0,0x0000 + b ..ppcMfspr_any_end + addi r3,r0,0x0000 + b ..ppcMfspr_any_end + addi r3,r0,0x0000 + b ..ppcMfspr_any_end + mfspr r3,0x3d3 + b ..ppcMfspr_any_end + mfspr r3,0x3d4 + b ..ppcMfspr_any_end + mfspr r3,0x3d5 + b ..ppcMfspr_any_end + mfspr r3,0x3d6 + b ..ppcMfspr_any_end + mfspr r3,0x3d7 + b ..ppcMfspr_any_end + mfspr r3,0x3d8 + b ..ppcMfspr_any_end + mfspr r3,0x3d9 + b ..ppcMfspr_any_end + mfspr r3,0x3da + b ..ppcMfspr_any_end + mfspr r3,0x3db + b ..ppcMfspr_any_end + mfspr r3,0x3dc + b ..ppcMfspr_any_end + mfspr r3,0x3dd + b ..ppcMfspr_any_end + mfspr r3,0x3de + b ..ppcMfspr_any_end + mfspr r3,0x3df + b ..ppcMfspr_any_end + mfspr r3,0x3e0 + b ..ppcMfspr_any_end + mfspr r3,0x3e1 + b ..ppcMfspr_any_end + mfspr r3,0x3e2 + b ..ppcMfspr_any_end + mfspr r3,0x3e3 + b ..ppcMfspr_any_end + mfspr r3,0x3e4 + b ..ppcMfspr_any_end + mfspr r3,0x3e5 + b ..ppcMfspr_any_end + mfspr r3,0x3e6 + b ..ppcMfspr_any_end + mfspr r3,0x3e7 + b ..ppcMfspr_any_end + mfspr r3,0x3e8 + b ..ppcMfspr_any_end + mfspr r3,0x3e9 + b ..ppcMfspr_any_end + mfspr r3,0x3ea + b ..ppcMfspr_any_end + mfspr r3,0x3eb + b ..ppcMfspr_any_end + mfspr r3,0x3ec + b ..ppcMfspr_any_end + mfspr r3,0x3ed + b ..ppcMfspr_any_end + mfspr r3,0x3ee + b ..ppcMfspr_any_end + mfspr r3,0x3ef + b ..ppcMfspr_any_end + mfspr r3,0x3f0 + b ..ppcMfspr_any_end + mfspr r3,0x3f1 + b ..ppcMfspr_any_end + mfspr r3,0x3f2 + b ..ppcMfspr_any_end + mfspr r3,0x3f3 + b ..ppcMfspr_any_end + mfspr r3,0x3f4 + b ..ppcMfspr_any_end + mfspr r3,0x3f5 + b ..ppcMfspr_any_end + mfspr r3,0x3f6 + b ..ppcMfspr_any_end + mfspr r3,0x3f7 + b ..ppcMfspr_any_end + mfspr r3,0x3f8 + b ..ppcMfspr_any_end + mfspr r3,0x3f9 + b ..ppcMfspr_any_end + mfspr r3,0x3fa + b ..ppcMfspr_any_end + mfspr r3,0x3fb + b ..ppcMfspr_any_end + mfspr r3,0x3fc + b ..ppcMfspr_any_end + mfspr r3,0x3fd + b ..ppcMfspr_any_end + mfspr r3,0x3fe + b ..ppcMfspr_any_end + mfspr r3,0x3ff + b ..ppcMfspr_any_end +..ppcMfspr_any_end: + mtlr r6 + blr + function_epilog(ppcMfspr_any) + +/*----------------------------------------------------------------------------+ +| PpcCachelinesize ++----------------------------------------------------------------------------*/ + function_prolog(ppcCachelinesize) + addi r3,r0,0x0080 + blr + function_epilog(ppcCachelinesize) + +/*----------------------------------------------------------------------------+ +| PpcProcid ++----------------------------------------------------------------------------*/ + function_prolog(ppcProcid) + addi r3,r0,0x03CA + blr + function_epilog(ppcProcid) + +/*----------------------------------------------------------------------------+ +| PpcMtmmucr ++----------------------------------------------------------------------------*/ + function_prolog(ppcMtmmucr) + blr + function_epilog(ppcMtmmucr) + +/*----------------------------------------------------------------------------+ +| PpcMttlb1 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMttlb1) + blr + function_epilog(ppcMttlb1) + +/*----------------------------------------------------------------------------+ +| PpcMttlb2 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMttlb2) + blr + function_epilog(ppcMttlb2) + +/*----------------------------------------------------------------------------+ +| PpcMttlb3 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMttlb3) + blr + function_epilog(ppcMttlb3) + +/*----------------------------------------------------------------------------+ +| PpcMftlb1 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMftlb1) + addis r3,r0,0xdead + ori r3,r3,0xbeef + blr + function_epilog(ppcMftlb1) + +/*----------------------------------------------------------------------------+ +| PpcMftlb2 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMftlb2) + addis r3,r0,0xdead + ori r3,r3,0xbeef + blr + function_epilog(ppcMftlb2) + +/*----------------------------------------------------------------------------+ +| PpcMftlb3 ++----------------------------------------------------------------------------*/ + function_prolog(ppcMftlb3) + addis r3,r0,0xdead + ori r3,r3,0xbeef + blr + function_epilog(ppcMftlb3) + +/*----------------------------------------------------------------------------+ +| PpcMfmmucr ++----------------------------------------------------------------------------*/ + function_prolog(ppcMfmmucr) + addis r3,r0,0xdead + ori r3,r3,0xbeef + blr + function_epilog(ppcMfmmucr) + +/*----------------------------------------------------------------------------+ +| PpcMfdcr_any ++----------------------------------------------------------------------------*/ + function_prolog(ppcMfdcr_any) + addis r3,r0,0xdead + ori r3,r3,0xbeef + blr + function_epilog(ppcMfdcr_any) + +/*----------------------------------------------------------------------------+ +| PpcMtdcr_any ++----------------------------------------------------------------------------*/ + function_prolog(ppcMtdcr_any) + blr + function_epilog(ppcMtdcr_any) + +/*----------------------------------------------------------------------------+ +| PpcIstrap. ++----------------------------------------------------------------------------*/ + function_prolog(ppcIstrap) + mfspr r3,srr1 + rlwinm. r3,r3,0,13,15 + bne ..is_trap + addi r3,r0,0x0000 + b ..is_return +..is_trap: + addi r3,r0,0x0001 +..is_return: + blr + function_epilog(ppcIstrap) + +/*----------------------------------------------------------------------------+ +| P_ptegg. r3=large page inidicator, r4=ea, r5 = sdr1, r6 = vsid. ++----------------------------------------------------------------------------*/ + function_prolog(p_ptegg) + cmpi cr0,1,r3,0x0000 + bne ..lp + addi r3,r0,12 + addi r8,r0,0x0001 + rlwinm r8,r8,16,0,31 + addi r8,r8,-1 + b ..ppast +..lp: addi r3,r0,24 + addi r8,r0,0x0001 + rlwinm r8,r8,4,0,31 + addi r8,r8,-1 + /*--------------------------------------------------------------------+ + | Only lower 39 bits of VSID are used in hash function. + +--------------------------------------------------------------------*/ +..ppast:rldicl r6,r6,0,25 + /*--------------------------------------------------------------------+ + | Discard page offset in effective address, only bits specified in + | the mask (r8) are used. + +--------------------------------------------------------------------*/ + srd r4,r4,r3 + and r4,r4,r8 + /*--------------------------------------------------------------------+ + | Perform hash function. + +--------------------------------------------------------------------*/ + xor r6,r6,r4 + /*--------------------------------------------------------------------+ + | 11 lowest bits from hash function are used directly. + +--------------------------------------------------------------------*/ + rlwinm r3,r6,7,14,24 + /*--------------------------------------------------------------------+ + | Shift output of the hash function by 11 bits. + +--------------------------------------------------------------------*/ + sradi r4,r6,11 + /*--------------------------------------------------------------------+ + | Calculate mask from sdr1.htabsize and AND it with upper 28 bits + | of the hash function result. + +--------------------------------------------------------------------*/ + rldicl r7,r5,0,59 + addi r8,r0,0x0001 + slw r8,r8,r7 + addi r8,r8,-1 + and r8,r8,r4 + /*--------------------------------------------------------------------+ + | Or in the 28+ 16 bits of the sdr1.htaborg. + +--------------------------------------------------------------------*/ + rldicl r5,r5,0,2 + addi r4,r0,0x0012 + srd r5,r5,r4 + or r4,r5,r8 + rldicr r4,r4,18,46 + or r3,r3,r4 + blr + function_epilog(p_ptegg) + +/*----------------------------------------------------------------------------+ +| S_ptegg. r3=large page inidicator, r4=ea, r5 = sdr1, r6 = vsid. ++----------------------------------------------------------------------------*/ + function_prolog(s_ptegg) + cmpi cr0,1,r3,0x0000 + bne ..lps + addi r3,r0,12 + addi r8,r0,0x0001 + rlwinm r8,r8,16,0,31 + addi r8,r8,-1 + b ..spast +..lps: addi r3,r0,24 + addi r8,r0,0x0001 + rlwinm r8,r8,4,0,31 + addi r8,r8,-1 + /*--------------------------------------------------------------------+ + | Only lower 39 bits of VSID are used in hash function. + +--------------------------------------------------------------------*/ +..spast:rldicl r6,r6,0,25 + /*--------------------------------------------------------------------+ + | Discard page offset in effective address, only bits specified in + | the mask (r8) are used. + +--------------------------------------------------------------------*/ + srd r4,r4,r3 + and r4,r4,r8 + /*--------------------------------------------------------------------+ + | Perform hash function. + +--------------------------------------------------------------------*/ + xor r6,r6,r4 + nand r6,r6,r6 + /*--------------------------------------------------------------------+ + | 11 lowest bits from hash function are used directly. + +--------------------------------------------------------------------*/ + rlwinm r3,r6,7,14,24 + /*--------------------------------------------------------------------+ + | Shift output of the hash function by 11 bits. + +--------------------------------------------------------------------*/ + sradi r4,r6,11 + /*--------------------------------------------------------------------+ + | Calculate mask from sdr1.htabsize and AND it with upper 28 bits + | of the hash function result. + +--------------------------------------------------------------------*/ + rldicl r7,r5,0,59 + addi r8,r0,0x0001 + slw r8,r8,r7 + addi r8,r8,-1 + and r8,r8,r4 + /*--------------------------------------------------------------------+ + | Or in the 28+ 16 bits of the sdr1.htaborg. + +--------------------------------------------------------------------*/ + rldicl r5,r5,0,2 + addi r4,r0,0x0012 + srd r5,r5,r4 + or r4,r5,r8 + rldicr r4,r4,18,46 + or r3,r3,r4 + blr + function_epilog(s_ptegg) + +/*----------------------------------------------------------------------------+ +| ppcLwsync. ++----------------------------------------------------------------------------*/ + function_prolog(ppcLwsync) + sync 1 + blr + function_epilog(ppcLwsync) + +/*----------------------------------------------------------------------------+ +| ppcPtesync. ++----------------------------------------------------------------------------*/ + function_prolog(ppcPtesync) + sync 2 + blr + function_epilog(ppcPtesync) + +/*----------------------------------------------------------------------------+ +| ppcTestandset. r3=address, r4=value. ++----------------------------------------------------------------------------*/ + function_prolog(ppcTestandset) +..again:lwarx r5,r0,r3 + cmpwi cr0,r5,0x0000 + bne ..again + stwcx. r4,r0,r3 + bne ..again + blr + function_epilog(ppcTestandset) + +/*----------------------------------------------------------------------------+ +| ppcSlbmte. ++----------------------------------------------------------------------------*/ + function_prolog(ppcSlbmte) + slbmte r3,r4 + blr + function_epilog(ppcSlbmte) + +/*----------------------------------------------------------------------------+ +| ppcSlbie. ++----------------------------------------------------------------------------*/ + function_prolog(ppcSlbie) + slbie r3 + blr + function_epilog(ppcSlbie) + +/*----------------------------------------------------------------------------+ +| ppcSlbia. ++----------------------------------------------------------------------------*/ + function_prolog(ppcSlbia) + slbia + blr + function_epilog(ppcSlbia) + +/*----------------------------------------------------------------------------+ +| ppcSlbmfev. ++----------------------------------------------------------------------------*/ + function_prolog(ppcSlbmfev) + slbmfev r3,r3 + blr + function_epilog(ppcSlbmfev) + +/*----------------------------------------------------------------------------+ +| ppcSlbmfee. ++----------------------------------------------------------------------------*/ + function_prolog(ppcSlbmfee) + slbmfee r3,r3 + blr + function_epilog(ppcSlbmfee) + +/*----------------------------------------------------------------------------+ +| ppcTlbiel. ++----------------------------------------------------------------------------*/ + function_prolog(ppcTlbiel) + TLBIEL(r3) + blr + function_epilog(ppcTlbiel) + +/*----------------------------------------------------------------------------+ +| PpcStvx ++----------------------------------------------------------------------------*/ + function_prolog(ppcStvx) + rlwinm r3,r3,3,19,29 + addi r3,r3,0x0010 + mflr r6 + bl ..vr_sett_lr +..vr_sett_lr: + mflr r5 + add r5,r5,r3 + mtlr r5 + blr + stvx 0,r0,r4 + b ..ppcStvx_any_end + stvx 1,r0,r4 + b ..ppcStvx_any_end + stvx 2,r0,r4 + b ..ppcStvx_any_end + stvx 3,r0,r4 + b ..ppcStvx_any_end + stvx 4,r0,r4 + b ..ppcStvx_any_end + stvx 5,r0,r4 + b ..ppcStvx_any_end + stvx 6,r0,r4 + b ..ppcStvx_any_end + stvx 7,r0,r4 + b ..ppcStvx_any_end + stvx 8,r0,r4 + b ..ppcStvx_any_end + stvx 9,r0,r4 + b ..ppcStvx_any_end + stvx 10,r0,r4 + b ..ppcStvx_any_end + stvx 11,r0,r4 + b ..ppcStvx_any_end + stvx 12,r0,r4 + b ..ppcStvx_any_end + stvx 13,r0,r4 + b ..ppcStvx_any_end + stvx 14,r0,r4 + b ..ppcStvx_any_end + stvx 15,r0,r4 + b ..ppcStvx_any_end + stvx 16,r0,r4 + b ..ppcStvx_any_end + stvx 17,r0,r4 + b ..ppcStvx_any_end + stvx 18,r0,r4 + b ..ppcStvx_any_end + stvx 19,r0,r4 + b ..ppcStvx_any_end + stvx 20,r0,r4 + b ..ppcStvx_any_end + stvx 21,r0,r4 + b ..ppcStvx_any_end + stvx 22,r0,r4 + b ..ppcStvx_any_end + stvx 23,r0,r4 + b ..ppcStvx_any_end + stvx 24,r0,r4 + b ..ppcStvx_any_end + stvx 25,r0,r4 + b ..ppcStvx_any_end + stvx 26,r0,r4 + b ..ppcStvx_any_end + stvx 27,r0,r4 + b ..ppcStvx_any_end + stvx 28,r0,r4 + b ..ppcStvx_any_end + stvx 29,r0,r4 + b ..ppcStvx_any_end + stvx 30,r0,r4 + b ..ppcStvx_any_end + stvx 31,r0,r4 + b ..ppcStvx_any_end +..ppcStvx_any_end: + mtlr r6 + blr + function_epilog(ppcStvx) + +/*----------------------------------------------------------------------------+ +| PpcLvxl ++----------------------------------------------------------------------------*/ + function_prolog(ppcLvxl) + rlwinm r3,r3,3,19,29 + addi r3,r3,0x0010 + mflr r6 + bl ..vr_gett_lr +..vr_gett_lr: + mflr r5 + add r5,r5,r3 + mtlr r5 + blr + lvxl 0,r0,r4 + b ..ppcLvxl_any_end + lvxl 1,r0,r4 + b ..ppcLvxl_any_end + lvxl 2,r0,r4 + b ..ppcLvxl_any_end + lvxl 3,r0,r4 + b ..ppcLvxl_any_end + lvxl 4,r0,r4 + b ..ppcLvxl_any_end + lvxl 5,r0,r4 + b ..ppcLvxl_any_end + lvxl 6,r0,r4 + b ..ppcLvxl_any_end + lvxl 7,r0,r4 + b ..ppcLvxl_any_end + lvxl 8,r0,r4 + b ..ppcLvxl_any_end + lvxl 9,r0,r4 + b ..ppcLvxl_any_end + lvxl 10,r0,r4 + b ..ppcLvxl_any_end + lvxl 11,r0,r4 + b ..ppcLvxl_any_end + lvxl 12,r0,r4 + b ..ppcLvxl_any_end + lvxl 13,r0,r4 + b ..ppcLvxl_any_end + lvxl 14,r0,r4 + b ..ppcLvxl_any_end + lvxl 15,r0,r4 + b ..ppcLvxl_any_end + lvxl 16,r0,r4 + b ..ppcLvxl_any_end + lvxl 17,r0,r4 + b ..ppcLvxl_any_end + lvxl 18,r0,r4 + b ..ppcLvxl_any_end + lvxl 19,r0,r4 + b ..ppcLvxl_any_end + lvxl 20,r0,r4 + b ..ppcLvxl_any_end + lvxl 21,r0,r4 + b ..ppcLvxl_any_end + lvxl 22,r0,r4 + b ..ppcLvxl_any_end + lvxl 23,r0,r4 + b ..ppcLvxl_any_end + lvxl 24,r0,r4 + b ..ppcLvxl_any_end + lvxl 25,r0,r4 + b ..ppcLvxl_any_end + lvxl 26,r0,r4 + b ..ppcLvxl_any_end + lvxl 27,r0,r4 + b ..ppcLvxl_any_end + lvxl 28,r0,r4 + b ..ppcLvxl_any_end + lvxl 29,r0,r4 + b ..ppcLvxl_any_end + lvxl 30,r0,r4 + b ..ppcLvxl_any_end + lvxl 31,r0,r4 + b ..ppcLvxl_any_end +..ppcLvxl_any_end: + mtlr r6 + blr + function_epilog(ppcLvxl) + +/*----------------------------------------------------------------------------+ +| PpcMfvscr ++----------------------------------------------------------------------------*/ + function_prolog(ppcMfvscr) + mfvscr 0 + blr + function_epilog(ppcMfvscr) + +/*----------------------------------------------------------------------------+ +| PpcMtvscr ++----------------------------------------------------------------------------*/ + function_prolog(ppcMtvscr) + mtvscr 0 + blr + function_epilog(ppcMtvscr) diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb index 3275aa297d..cf7b2a389a 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Options.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb @@ -137,5 +137,6 @@ default _ROMSTART=0xfff03000 ## linuxBIOS C code runs at this location in RAM default _RAMBASE=0x00100000 +default CROSS_COMPILE="powerpc-405-linux-gnu-" ### End Options.lb end diff --git a/src/mainboard/momentum/apache/Config.lb b/src/mainboard/momentum/apache/Config.lb index 45d41dda38..488f7d1e84 100644 --- a/src/mainboard/momentum/apache/Config.lb +++ b/src/mainboard/momentum/apache/Config.lb @@ -5,60 +5,61 @@ ## ## Early board initialization, called from ppc_main() ## -#initobject init.c +initobject init.c +initobject mainboard.c +initobject boardutil.c +initobject timerspeed.S arch ppc end chip northbridge/ibm/cpc925 device pci_domain 0 on - device pci 00.0 on end - device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # pxhd1 - device pci 00.0 on end - device pci 00.1 on end - device pci 00.2 on - chip drivers/generic/generic - device pci 04.0 on end - device pci 04.1 on end - end + chip southbridge/amd/amd8131 + device pci 01.0 on #PCI-X Bridge + chip drivers/pci/onboard #intel GD31244 chip + device pci 01.0 on end #SATA controller + end + end + device pci 01.1 on end #APIC controller + device pci 02.0 on end #PCI-X Bridge + device pci 02.1 on end #APIC controller + device pci 03.0 on #PCI-X Bridge + chip drivers/pci/onboard #intel i82546EB chip + device pci 01.0 on end #GB Ethernet 0 + device pci 01.1 on end #GB Ethernet 1 end - device pci 00.3 on end end - end - device pci 06.0 on end - chip southbridge/intel/ich5r # ich5r - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 off end - device pci 1d.7 on end - device pci 1e.0 on + device pci 03.1 on end #APIC controller + device pci 04.0 on end #PCI-X Bridge + device pci 04.1 on end #APIC controller + end #amd8131 + + chip southbridge/amd/amd8111 + device pci 5.0 on #PCI Bridge + device pci 0.0 on end #USB Controller 0 + device pci 0.1 on end #USB Controller 1 + device pci 0.2 on end #USB Controller 2 + device pci 1.0 on end #10/100 Ethernet Controller chip drivers/ati/ragexl - device pci 0c.0 on end + device pci 3.0 on end # ATI Rage Video Controller end end - device pci 1f.0 on - chip superio/NSC/pc87427 + device pci 6.0 on #ISA Bridge/LPC Controller + chip superio/NSC/pc87427 #NSC Super IO chip device pnp 2e.0 off end device pnp 2e.2 on -# io 0x60 = 0x2f8 -# irq 0x70 = 3 - io 0x60 = 0x3f8 + io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 on -# io 0x60 = 0x3f8 -# irq 0x70 = 4 - io 0x60 = 0x2f8 + io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.4 off end device pnp 2e.5 off end device pnp 2e.6 on - io 0x60 = 0x60 - io 0x62 = 0x64 + io 0x60 = 0x60 + io 0x62 = 0x64 irq 0x70 = 1 end device pnp 2e.7 off end @@ -67,36 +68,18 @@ chip northbridge/ibm/cpc925 device pnp 2e.f on end device pnp 2e.10 off end device pnp 2e.14 off end - end - end - device pci 1f.1 on end - device pci 1f.2 off end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end - register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO" - register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW" - register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT" - end - end - device apic_cluster 0 on - chip cpu/ppc/ppc970 # cpu 0 - end - chip cpu/ppc/ppc970 # cpu 1 - end - end -end - + end #NSC Super IO chip + end #ISA Bridge/LPC + device pci 6.1 on end #IDE Controller + device pci 6.2 on end #SMBus Controller + device pci 6.3 on end #ACPI + device pci 6.5 off end #AC97 Audio + device pci 6.6 off end #MC97 Modem + end #amd8111 + end #pci domain 0 +end #cpc925 -chip cpu/ppc/ppc4xx - device pci_domain 0 on - device pci 0.0 on end - chip southbridge/winbond/w83c553 - device pci 9.0 on end # ISA bridge - device pci 9.1 on end # IDE contoller - end - device pci e.0 on end - end +chip cpu/ppc/ppc970 end ## diff --git a/src/mainboard/momentum/apache/boardutil.c b/src/mainboard/momentum/apache/boardutil.c new file mode 100644 index 0000000000..370d1a47e5 --- /dev/null +++ b/src/mainboard/momentum/apache/boardutil.c @@ -0,0 +1,406 @@ +/* + * Copyright (C) 2003, Greg Watson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * Do very early board initialization: + * + * - Configure External Bus (EBC) + * - Setup Flash + * - Setup NVRTC + * - Setup Board Control and Status Registers (BCSR) + * - Enable UART0 for debugging + */ + +#include "boardutil.h" +#include "ppc970lib.h" +#include "ppc970.h" +#include "stddef.h" +#include "string.h" + +/*----------------------------------------------------------------------------+ +| What_platform. ++----------------------------------------------------------------------------*/ +int what_platform() +{ + + #ifdef PPC970FX_EVB_LITE + return(PLATFORM_EVB_LITE); + #endif + #ifdef PPC970FX_EVB + return(PLATFORM_EVB_FINAL); + #endif +} + +/*----------------------------------------------------------------------------+ +| Get_system_info. Cannot access any global variables in this function. ++----------------------------------------------------------------------------*/ +void get_system_info(board_cfg_data_t *board_cfg) +{ + + unsigned long msr; + unsigned long data; + + if (board_cfg==NULL) { + (void)ppcHalt(); + } + msr=ppcAndMsr((unsigned long)~MSR_EE); + board_cfg->usr_config_ver[0]='1'; + board_cfg->usr_config_ver[1]='.'; + board_cfg->usr_config_ver[2]='0'; + board_cfg->usr_config_ver[3]='\0'; + /*-------------------------------------------------------------------------+ + | Read power status register. + +-------------------------------------------------------------------------*/ + data=read_psr()&SCOM_PSR_FREQ_MASK; + if (data==SCOM_PSR_FREQ_FULL) { + board_cfg->freq_ratio=1; + } else if (data==SCOM_PSR_FREQ_HALF) { + board_cfg->freq_ratio=2; + } else if (data==SCOM_PSR_FREQ_QUARTER) { + board_cfg->freq_ratio=4; + } else { + board_cfg->freq_ratio=0; + } + /*-------------------------------------------------------------------------+ + | Read information passed from service processor. + +-------------------------------------------------------------------------*/ + if (get_ei_ratio(&data)==0) { + board_cfg->ei_ratio=data; + } else { + board_cfg->ei_ratio=0; + } + if (get_sys_clk(&data)==0) { + board_cfg->sys_freq=data; + } else { + board_cfg->sys_freq=0; + } + if (get_pll_mult(&data)==0) { + if (board_cfg->freq_ratio!=0) { + board_cfg->cpu_freq=(board_cfg->sys_freq* data)/ board_cfg->freq_ratio; + } else { + board_cfg->cpu_freq=0; + } + } else { + data=0; + board_cfg->cpu_freq=0; + } + /*-------------------------------------------------------------------------+ + | On some boards we have to execute with timers running on internal clock. + +-------------------------------------------------------------------------*/ + if ((ppcMfspr_any(SPR_HID0)&HID0_EXT_TB_EN)==0) { + board_cfg->tmr_freq=(board_cfg->sys_freq* data)/ PPC970_TB_RATIO; + } else { + board_cfg->tmr_freq=EXT_TIME_BASE_FREQ; + } + /*-------------------------------------------------------------------------+ + | If the above calculation did not yield valid timer speed try to estimate + | it. + +-------------------------------------------------------------------------*/ + if (board_cfg->tmr_freq==0) { + board_cfg->tmr_freq=timebase_speed_calc(UART1_MMIO_BASE); + } + /*-------------------------------------------------------------------------+ + | Read information passed from service processor. + +-------------------------------------------------------------------------*/ + board_cfg->mem_size=sdram_size(); + /*-------------------------------------------------------------------------+ + | Assign rest of the information. + +-------------------------------------------------------------------------*/ + board_cfg->ser_freq=UART_INPUT_CLOCK; + board_cfg->procver=ppcMfspr_any(SPR_PVR); + board_cfg->hid0=ppcMfspr_any(SPR_HID0); + board_cfg->hid1=ppcMfspr_any(SPR_HID1); + board_cfg->hid4=ppcMfspr_any(SPR_HID4); + board_cfg->hid5=ppcMfspr_any(SPR_HID5); + board_cfg->hior=ppcMfspr_any(SPR_HIOR); + board_cfg->sdr1=ppcMfspr_any(SPR_SDR1); + board_cfg->procstr[0]='9'; + board_cfg->procstr[1]='7'; + board_cfg->procstr[2]='0'; + board_cfg->procstr[3]='F'; + board_cfg->procstr[4]='X'; + board_cfg->procstr[5]='\0'; + board_cfg->reserved[0]='\0'; + (void)get_hwd_addr((char *)board_cfg->hwaddr0, 0); + (void)ppcMtmsr(msr); + return; +} + +/*----------------------------------------------------------------------------+ +| Get_hwd_addr. ++----------------------------------------------------------------------------*/ +int get_hwd_addr(char *dest, + int ethernet_num) +{ + + bios_data_struct_t *bios_data; + char *src; + unsigned char nc; + int len; + int num; + + bios_data=(bios_data_struct_t *)PIBS_DATABASE_ADDR; + if (ethernet_num!=0) { + for(len=0;lenbios_eth_hwd0; + } + len=0; + while((src[len]!='\0') && (len<(ETHERNET_HW_ADDR_LEN* 3))) { + len++; + } + if (len!=(ETHERNET_HW_ADDR_LEN* 2)) { + for(len=0;len='0') && (nc<='9')) { + num=nc- '0'; + } else if ((nc>='A') && (nc<='F')) { + num=nc- 'A'+ 0xA; + } else { + for(len=0;len=BOOT_BASE) && (addr=BOOT_BASE) { + return(0); + } + return(1); +} + diff --git a/src/mainboard/momentum/apache/boardutil.h b/src/mainboard/momentum/apache/boardutil.h new file mode 100755 index 0000000000..893a147793 --- /dev/null +++ b/src/mainboard/momentum/apache/boardutil.h @@ -0,0 +1,154 @@ + +#ifndef _boardutil_h_ +#define _boardutil_h_ + + +/*----------------------------------------------------------------------------+ +| Board specific defines. ++----------------------------------------------------------------------------*/ +#define FLASH_INTEL_SECTORSIZE 0x00020000 +#define FLASH_AMD_SECTORSIZE 0x00010000 +#define PIBS2_MAX_SIZE 0x000E0000 +#define PIBS_DATABASE_SIZE 0x00020000 +#define PIBS_DATABASE_ADDR 0x00000000FFFE0000UL + +#define PIBS_DATA_FIELDSIZE 256 +#define ETHERNET_HW_ADDR_LEN 6 + +/*----------------------------------------------------------------------------+ +| Current board settings. ++----------------------------------------------------------------------------*/ +typedef struct board_cfg_data { + char usr_config_ver[4]; + unsigned char reserved[28]; + unsigned long tmr_freq; + unsigned long mem_size; + unsigned long ei_ratio; + unsigned long sys_freq; + unsigned long cpu_freq; + unsigned long freq_ratio; + unsigned long ser_freq; + unsigned long procver; + unsigned long hid0; + unsigned long hid1; + unsigned long hid4; + unsigned long hid5; + unsigned long hior; + unsigned long sdr1; + char procstr[16]; + unsigned char hwaddr0[ETHERNET_HW_ADDR_LEN]; + unsigned char pad_size[2]; +} board_cfg_data_t; + +/*----------------------------------------------------------------------------+ +| PIBS data CPU2. ++----------------------------------------------------------------------------*/ +typedef struct cpu_data { + unsigned long img_srr0; + unsigned long img_srr1; + unsigned long r3_value; + unsigned long img_valid; +} cpu_data_t; + +/*----------------------------------------------------------------------------+ +| PIBS data. ++----------------------------------------------------------------------------*/ +typedef struct bios_data_struct { + /*-------------------------------------------------------------------------+ + | Is this data section valid? [TRUE|FALSE] string. + +-------------------------------------------------------------------------*/ + char bios_data_valid[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | Information about the main PIBS board image [TRUE|FALSE] string. + +-------------------------------------------------------------------------*/ + char pibs2_valid[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | Autoboot configuration. + +-------------------------------------------------------------------------*/ + char autoboot_parm[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | Configuration. + +-------------------------------------------------------------------------*/ + char bios_eth_hwd0[PIBS_DATA_FIELDSIZE]; + char ifconfig_parm0[PIBS_DATA_FIELDSIZE]; + char route_parm[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | TFTP information. + +-------------------------------------------------------------------------*/ + char bios_tftp_fname[PIBS_DATA_FIELDSIZE]; + char bios_tftp_destip[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | Chip and board clocking information. + +-------------------------------------------------------------------------*/ + char clocking_valid[PIBS_DATA_FIELDSIZE]; + char clocking_parm[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | User data, alias list, autoboot delay, dhcp flag. + +-------------------------------------------------------------------------*/ + char user_data[PIBS_DATA_FIELDSIZE]; + char aliaslist[PIBS_DATA_FIELDSIZE]; + char autoboot_delay[PIBS_DATA_FIELDSIZE]; + char dhcp0[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | HT link optimization variable. + +-------------------------------------------------------------------------*/ + char opthtlink[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | Indicates IDE cable type. + +-------------------------------------------------------------------------*/ + char ide80wire[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | Automatically initialize IDE. + +-------------------------------------------------------------------------*/ + char initide[PIBS_DATA_FIELDSIZE]; + /*-------------------------------------------------------------------------+ + | OpenFirmware interface private variable + +-------------------------------------------------------------------------*/ + char openfirmware[PIBS_DATA_FIELDSIZE]; +} bios_data_struct_t; + +/*----------------------------------------------------------------------------+ +| Function prototypes. ++----------------------------------------------------------------------------*/ +void get_system_info( + board_cfg_data_t *board_cfg ); + +int get_hwd_addr( + char *dest, + int ethernet_num ); + +int get_sys_clk( + unsigned long *value ); + +int get_pll_mult( + unsigned long *value ); + +int get_ei_ratio( + unsigned long *value ); + +int read_sp_data( + unsigned int offset, + unsigned int count, + unsigned long *data ); + +int write_sp_data( + unsigned int offset, + unsigned int data ); + +unsigned long read_psr( + void ); + +void write_pcr_pcrh( + unsigned long data ); + +int is_writable( + unsigned long addr, + unsigned long len ); + +void super_io_setup( + void ); + +unsigned long sdram_size( + void ); + +#endif /* _boardutil_h_ */ diff --git a/src/mainboard/momentum/apache/init.c b/src/mainboard/momentum/apache/init.c new file mode 100644 index 0000000000..3a7aed7774 --- /dev/null +++ b/src/mainboard/momentum/apache/init.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2003, Greg Watson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * Do very early board initialization: + * + * - Setup SIO + */ +#include "ppc970.h" +#include "boardutil.h" + +/*----------------------------------------------------------------------------+ +| Local defines. ++----------------------------------------------------------------------------*/ +#define BASE_MASK 0xFFFFFFFF + +void +board_init(void) +{ + super_io_setup(); +} + + +/*----------------------------------------------------------------------------+ +| Super_io_setup. ++----------------------------------------------------------------------------*/ +void super_io_setup() +{ + + unsigned long io_base; + unsigned long sio_index; + unsigned long sio_data; + int platform; + unsigned int i; + + /*-------------------------------------------------------------------------+ + | If this is not a JS20 or EVB platform then just return. + +-------------------------------------------------------------------------*/ + platform=what_platform(); + if (platform==PLATFORM_EVB_FINAL) { + /*----------------------------------------------------------------------+ + | Assign addresses. + +----------------------------------------------------------------------*/ + io_base=(unsigned long)(NB_HT_IO_BASE_BYTE<>8)&0xFF)); + (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB); + (void)outbyte(sio_data, (unsigned int)((UART0_MMIO_BASE>>0)&0xFF)); + (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL); + (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE); + /*----------------------------------------------------------------------+ + | Serial 2 setup/enable. + +----------------------------------------------------------------------*/ + (void)outbyte(sio_index, SUPER_IO_DEVICE_SEL); + (void)outbyte(sio_data, SUPER_IO_DEVICE_S2); + (void)outbyte(sio_index, SUPER_IO_BASE_DEV_MSB); + (void)outbyte(sio_data, (unsigned int)((UART1_MMIO_BASE>>8)&0xFF)); + (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB); + (void)outbyte(sio_data, (unsigned int)((UART1_MMIO_BASE>>0)&0xFF)); + (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL); + (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE); + /*----------------------------------------------------------------------+ + | X-bus setup/enable. + +----------------------------------------------------------------------*/ + (void)outbyte(sio_index, SUPER_IO_DEVICE_SEL); + (void)outbyte(sio_data, SUPER_IO_DEVICE_XBUS); + (void)outbyte(sio_index, SUPER_IO_BASE_DEV_MSB); + (void)outbyte(sio_data, (SUPER_IO_ADDR_XBUS>>8)&0xFF); + (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB); + (void)outbyte(sio_data, (SUPER_IO_ADDR_XBUS>>0)&0xFF); + (void)outbyte(sio_index, SUPER_IO_XBUS_CONFIG); + (void)outbyte(sio_data, SUPER_IO_BIOS_SIZE_1M); + (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL); + (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE); + for(i=0;i<16;i++) { + (void)outbyte(io_base+ SUPER_IO_XBUS_HOST_ACCESS, i); + } + /*----------------------------------------------------------------------+ + | RTC setup/enable. + +----------------------------------------------------------------------*/ + (void)outbyte(sio_index, SUPER_IO_DEVICE_SEL); + (void)outbyte(sio_data, SUPER_IO_DEVICE_RTC); + (void)outbyte(sio_index, SUPER_IO_BASE_DEV_MSB); + (void)outbyte(sio_data, (SUPER_IO_ADDR_RTC>>8)&0xFF); + (void)outbyte(sio_index, SUPER_IO_BASE_DEV_LSB); + (void)outbyte(sio_data, (SUPER_IO_ADDR_RTC>>0)&0xFF); + (void)outbyte(sio_index, SUPER_IO_EXT_DEV_MSB); + (void)outbyte(sio_data, (SUPER_IO_ADDR_NVRAM>>8)&0xFF); + (void)outbyte(sio_index, SUPER_IO_EXT_DEV_LSB); + (void)outbyte(sio_data, (SUPER_IO_ADDR_NVRAM>>0)&0xFF); + (void)outbyte(sio_index, SUPER_IO_RTC_DATE_ALARM_OFF); + (void)outbyte(sio_data, SUPER_IO_RTC_DATE_ALARM_LOC); + (void)outbyte(sio_index, SUPER_IO_RTC_MONTH_ALARM_OFF); + (void)outbyte(sio_data, SUPER_IO_RTC_MONTH_ALARM_LOC); + (void)outbyte(sio_index, SUPER_IO_RTC_CENTURY_ALARM_OFF); + (void)outbyte(sio_data, SUPER_IO_RTC_CENTURY_ALARM_LOC); + (void)outbyte(sio_index, SUPER_IO_DEVICE_CTRL); + (void)outbyte(sio_data, SUPER_IO_DEVICE_ENABLE); + } + return; +} + +void +board_init2(void) +{ +} diff --git a/src/mainboard/momentum/apache/mainboard.c b/src/mainboard/momentum/apache/mainboard.c new file mode 100644 index 0000000000..1ba9120a48 --- /dev/null +++ b/src/mainboard/momentum/apache/mainboard.c @@ -0,0 +1,12 @@ +#include +#include +#include +#include +#include +#include "chip.h" + +#if CONFIG_CHIP_NAME == 1 +struct chip_operations mainboard_tyan_s2735_ops = { + CHIP_NAME("Momentum Apache mainboard") +}; +#endif diff --git a/src/mainboard/momentum/apache/ppc970fx.h b/src/mainboard/momentum/apache/ppc970fx.h deleted file mode 100644 index 8745fd2f1e..0000000000 --- a/src/mainboard/momentum/apache/ppc970fx.h +++ /dev/null @@ -1,1191 +0,0 @@ -/*bsp_970fx/include/ppc970fx_board.h, pibs_970, pibs_970_1.0 2/24/05 08:04:58*/ -/*----------------------------------------------------------------------------+ -| COPYRIGHT I B M CORPORATION 2000, 2004 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -| US Government Users Restricted Rights - Use, duplication or -| disclosure restricted by GSA ADP Schedule Contract with -| IBM Corp. -+----------------------------------------------------------------------------*/ -/*----------------------------------------------------------------------------+ -| PPC970FX BSP for EPOS -| Author: Maciej P. Tyrlik -| Component: Include file. -| File: ppc970fx_board.h -| Purpose: Board chip dependent defines. Header file defining PPC970FX and -| PPC970FX eval board constants. "#define" statements can be placed -| in this file since it is included from assembler. -| Changes: -| Date Comment: -| --------- -------- -| 14-Sep-00 Created MPT -| 05-Jan-01 Added defines for "real serial port address" MPT -| 09-Jan-01 Removed C++ defines that caused problems with XCOFF compilerMPT -| 06-Mar-01 Chenged location of the serial ports MPT -| 19-Mar-01 Chenged location of the serial ports MPT -| 19-Jul-01 Chenged BRDC registr location and added ZMII address MPT -| 14-Feb-02 Added DMA stuff MPT -| 18-Jul-02 Port to 405LP Arctic MPT -| 25-Jul-02 Added all the Core library definitions DWG -| 29-Aug-02 Added all Ready Timeout Count (RTC) options to EBC0_CFG DWG -| 30-Sep-02 Added new clocking bits for pass 2 MPT -| 27-Jan-03 Port to 7XXFX MPT -| 04-Feb-03 Add divisor for UART SCC -| 04-Feb-03 Added MV64360 Reg Defines & Changed UART MMIO Base CRB -| 24-Apr-03 Updated for CPLD revisions MPT -| 29-May-03 Add PCI related defines SCC -| 06-Aug-03 Port to Buckeye SCC -| 08-Sep-03 More changes for MV64460 on Buckeye MCG -| 12-Sep-03 Moved all PVR #defines here from other files MCG -| 16-Sep-03 Added MV64460 MPP register offsets MCG -| 31-Oct-03 Added SRAM_CFG bit definitions, Ethernet BAx bit defs MCG -| 31-Oct-03 Lowered max RX burst length for Ethernet cache coherency MCG -| 08-Dec-03 New defines PCI P2P regs, interrupt cause/mask regs MCG -| 04-Feb-04 All new for PPC970FX MPT -+----------------------------------------------------------------------------*/ - -#ifndef _PPC970FX_H_ -#define _PPC970FX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------------------------+ -| Processor Version Register (PVR) values -+----------------------------------------------------------------------------*/ -#define PVR_970 0x0039 /* 970 any revision*/ -#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */ -#define PVR_970FX 0x003C /* 970FX any revision*/ -#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */ -#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */ -#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */ -#define PVR_RESERVED 0x000000F0 /* reserved nibble */ - -/*----------------------------------------------------------------------------+ -| Supported platforms. -+----------------------------------------------------------------------------*/ -#define PLATFORM_G5 0 -#define PLATFORM_NEW_JS20 2 -#define PLATFORM_EVB_LITE 3 -#define PLATFORM_EVB_FINAL 4 -#define PLATFORM_APACHE 5 - -/*----------------------------------------------------------------------------+ -| When timers are running based on CPU speed this is the timer to CPU frequency -| ratio. -+----------------------------------------------------------------------------*/ -#define PPC970_TB_RATIO 8 - -/*----------------------------------------------------------------------------+ -| Cache line size. -+----------------------------------------------------------------------------*/ -#define CACHE_LINE_SIZE_L1 128 -#define CACHE_LINE_SIZE_L2 128 - -/*----------------------------------------------------------------------------+ -| SLB size. -+----------------------------------------------------------------------------*/ -#define SLB_SIZE 64 - -/*----------------------------------------------------------------------------+ -| TLB size. -+----------------------------------------------------------------------------*/ -#define TLB_SIZE 1024 - -/*----------------------------------------------------------------------------+ -| Partial memory map. -+----------------------------------------------------------------------------*/ -#define SDRAM_BASE 0x0000000000000000UL -#define SDRAM_SIZE 0x0000000080000000UL -#define IO_BASE 0x0000000080000000UL -#define IO_SIZE 0x0000000080000000UL -#define PCI_BUS_MEM_BASE 0x0000000080000000UL -#define PCI_BUS_MEM_SIZE 0x0000000070000000UL -#define PCI0_BASE 0x00000000F0000000UL -#define PCI0_SIZE 0x0000000002000000UL -#define HT1_BASE 0x00000000F2000000UL -#define HT1_SIZE 0x0000000003000000UL -#define PPC925_BASE 0x00000000F8000000UL -#define PPC925_SIZE 0x0000000001000000UL -#define SB_IOAPIC_BASE 0x00000000FEC00000UL -#define BOOT_BASE 0x00000000FF000000UL -#define BOOT_BASE_AS 0x00000000FF000000 -#define BOOT_END 0x00000000FFFFFFFFUL -#define FLASH_BASE_INTEL 0x00000000FF800000UL -#define FLASH_BASE_INTEL_AS 0x00000000FF800000 -#define FLASH_BASE_AMD 0x00000000FFF00000UL -#define FLASH_BASE_AMD_AS 0x00000000FFF00000 -#define SDRAM_UPPER_BASE 0x0000000100000000UL -#define SDRAM_UPPER_SIZE 0x0000000F00000000UL - -/*----------------------------------------------------------------------------+ -| BOOT_STACK_ADDR is data used for stack before SDRAM is available. This data -| will be written to memory after the SDRAM is initialized. All values here -| must be less than 32 bits. Following 14 defines need to be changed when -| changing the location of PIBS in SDRAM (the link file also need to be -| changed in order to fully relocate PIBS. -+----------------------------------------------------------------------------*/ -#define PIBS_BASE_ADDR 0x00C00000 -#define BOOT_STACK_ADDR 0x00CE0000 -#define BOOT_STACK_SIZE 0x00004000 -#define MEM_CHK_START_ADDR 0x00C40000 -#define MEM_CHK_SIZE 0x00008000 - -/*----------------------------------------------------------------------------+ -| Address of a CPU0, CPU1 shared memory structure. -+----------------------------------------------------------------------------*/ -#define CPU1_DATA_STRUCT_ADDR 0x00C00040 -#define CPU1_DATA_STRUCT_SRR0_OFF 0x00000000 -#define CPU1_DATA_STRUCT_SRR1_OFF 0x00000008 -#define CPU1_DATA_STRUCT_R3_OFF 0x00000010 -#define CPU1_DATA_STRUCT_VALID_OFF 0x00000018 -#define CPU1_DATA_STRUCT_DEL_VALID_OFF 0x00000020 - -/*----------------------------------------------------------------------------+ -| Address of the memory location used for the test and set instruction -| sequence. -+----------------------------------------------------------------------------*/ -#define VM_TEST_AND_SET_ADDR 0x0000000000C000F0UL - -/*----------------------------------------------------------------------------+ -| Initial page table address. -+----------------------------------------------------------------------------*/ -#define INITIAL_PAGE_TABLE_ADDR_CPU0 0x0000000000D00000 -#define INITIAL_PAGE_TABLE_ADDR_CPU1 0x0000000000D40000 -#define INITIAL_PAGE_TABLE_SIZE 0x0000000000040000 - -/*----------------------------------------------------------------------------+ -| Initial stack size. Must be less than 32 bits in length. -+----------------------------------------------------------------------------*/ -#define MY_MAIN_STACK_SIZE (8* 1024) - -/*----------------------------------------------------------------------------+ -| PCI prefetchable and non-prefetchable master memory windows. -| The prefetchable region is large enough to cover 2GB of CPC925 attached -| SDRAM plus space for other devices on the bus. -+----------------------------------------------------------------------------*/ -#define PCI_MEM_PF_CPU_ADDR 0x00000000 -#define PCI_MEM_PF_PCI_ADDR 0x00000000 -#define PCI_MEM_PF_SIZE 0xA0000000 -#define PCI_MEM_NPF_CPU_ADDR 0xA0000000 -#define PCI_MEM_NPF_PCI_ADDR 0xA0000000 -#define PCI_MEM_NPF_SIZE 0x20000000 - -/*----------------------------------------------------------------------------+ -| Serial port address. The base address must be programmed into super I/O. The -| external time base is available only on JS20. -+----------------------------------------------------------------------------*/ -#if defined(PPC970FX_EVB) || defined(PPC970FX_APACHE) -#define UART1_MMIO_BASE 0xF40002F8UL -#define UART0_MMIO_BASE 0xF40003F8UL -#define UART1_MMIO_OFFSET 0x2F8; -#define UART0_MMIO_OFFSET 0x3F8; -#define UART_INPUT_CLOCK 1843200 -#define EXT_TIME_BASE_FREQ 0 -#define DIV_HIGH_9600 0x00 -#define DIV_LOW_9600 0x0C -#endif - -#ifdef PPC970FX_EVB_LITE -#define UART1_MMIO_BASE 0xF40002F8UL -#define UART0_MMIO_BASE 0xF40003F8UL -#define UART1_MMIO_OFFSET 0x2F8; -#define UART0_MMIO_OFFSET 0x3F8; -#define UART_INPUT_CLOCK 1843200 -#define EXT_TIME_BASE_FREQ 0 -#define DIV_HIGH_9600 0x00 -#define DIV_LOW_9600 0x0C -#endif - -#ifdef PPC970FX_JS20 -#define UART1_MMIO_BASE 0xF40002F8UL -#define UART0_MMIO_BASE 0xF40003F8UL -#define UART1_MMIO_OFFSET 0x2F8; -#define UART0_MMIO_OFFSET 0x3F8; -#define UART_INPUT_CLOCK 1843200 -#define EXT_TIME_BASE_FREQ 14318000 -#define DIV_HIGH_9600 0x00 -#define DIV_LOW_9600 0x0C -#endif - -/*----------------------------------------------------------------------------+ -| In case of G5 PCI serial card. G5 uses external time base frequency. -+----------------------------------------------------------------------------*/ -#ifdef PPC970FX_G5 -#define UART1_MMIO_BASE 0xF40000F0UL -#define UART0_MMIO_BASE 0xF4010000UL -#define UART1_MMIO_OFFSET 0x000000F0; -#define UART0_MMIO_OFFSET 0x00010000; -#define UART_INPUT_CLOCK 14745600 -#define EXT_TIME_BASE_FREQ 33333333 -#define DIV_HIGH_9600 0x00 -#define DIV_LOW_9600 0x60 -#endif - -#define EXT_IRQ_COM1 EXT_SB_HT4 -#define EXT_IRQ_COM2 EXT_SB_HT3 - -/*----------------------------------------------------------------------------+ -| Locations in Super I/O NVRAM where service processor stores information for -| the PPC970FX CPU. -+----------------------------------------------------------------------------*/ -#define SUPER_IO_NVRAM_TEMP0 16 -#define SUPER_IO_NVRAM_TEMP1 (SUPER_IO_NVRAM_TEMP0+ 4) -#define SUPER_IO_NVRAM_TEMP2 (SUPER_IO_NVRAM_TEMP1+ 4) -#define SUPER_IO_NVRAM_TEMP3 (SUPER_IO_NVRAM_TEMP2+ 4) -#define SUPER_IO_NVRAM_TEMP4 (SUPER_IO_NVRAM_TEMP3+ 4) -#define SUPER_IO_NVRAM_TEMP5 (SUPER_IO_NVRAM_TEMP4+ 4) -#define SUPER_IO_NVRAM_TEMP6 (SUPER_IO_NVRAM_TEMP5+ 4) -#define SUPER_IO_NVRAM_TEMP7 (SUPER_IO_NVRAM_TEMP6+ 4) -#define SUPER_IO_NVRAM_TEMP_VALID (SUPER_IO_NVRAM_TEMP7+ 4) - -#define SUPER_IO_NVRAM_DATA_VALID 64 -#define SUPER_IO_NVRAM_SYS_CLK (SUPER_IO_NVRAM_DATA_VALID+ 0x04) -#define SUPER_IO_NVRAM_CLK_MULT (SUPER_IO_NVRAM_SYS_CLK+ 0x04) -#define SUPER_IO_NVRAM_EI_RATIO (SUPER_IO_NVRAM_CLK_MULT+ 0x01) - -#define SUPER_IO_VALID_VALUE 0x426F4F6D - -#define PPC970_EI_RATIO_000 2 -#define PPC970_EI_RATIO_001 3 -#define PPC970_EI_RATIO_010 4 -#define PPC970_EI_RATIO_011 6 -#define PPC970_EI_RATIO_100 8 -#define PPC970_EI_RATIO_101 12 -#define PPC970_EI_RATIO_110 16 - -/*----------------------------------------------------------------------------+ -| Locations in Super I/O NVRAM where PPC970 store commands for service -| processor. 0x01 is written by PPC970 to initiate action by the service -| processor. This value is cleared by the service processor upon receiving -| the command. -+----------------------------------------------------------------------------*/ -#define SUPER_IO_NVRAM_POWER_OFF 96 -#define SUPER_IO_NVRAM_RESTART (SUPER_IO_NVRAM_POWER_OFF+ 0x2) - -/*----------------------------------------------------------------------------+ -| Default HID register settings. -+----------------------------------------------------------------------------*/ -#define HID0_PREFEAR 0x0011008180000000 -#define HID1_PREFEAR 0xFD3C200000000000 -#define HID4_PREFEAR 0x0000001000000000 -#define HID5_PREFEAR 0x0000000000000080 - -/*----------------------------------------------------------------------------+ -| Power control SCOM register definitions. -+----------------------------------------------------------------------------*/ -#define SCOM_ADDR_PCR_WRITE 0x000000000AA00000UL -#define SCOM_ADDR_PCR_WRITE_ASM 0x000000000AA00000 -#define SCOM_ADDR_PSR_READ 0x0000000040808000UL -#define SCOM_ADDR_PSR_READ_ASM 0x0000000040808000 - -#define SCOM_ADDR_PCR_DATA_MASK 0x0000000080000000UL -#define SCOM_ADDR_PCR_DATA_MASK_ASM 0x0000000080000000 - -#define SCOM_ADDR_PCR_FREQ_VALID 0x0000000000010000UL -#define SCOM_ADDR_PCR_FREQ_FULL 0x0000000000000000UL -#define SCOM_ADDR_PCR_FREQ_HALF 0x0000000000020000UL -#define SCOM_ADDR_PCR_FREQ_QUARTER 0x0000000000040000UL - -#define SCOM_PSR_FREQ_MASK 0x0300000000000000UL -#define SCOM_PSR_FREQ_FULL 0x0000000000000000UL -#define SCOM_PSR_FREQ_HALF 0x0100000000000000UL -#define SCOM_PSR_FREQ_QUARTER 0x0200000000000000UL -#define SCOM_PSR_COMM_COMPLETED 0x1000000000000000UL -#define SCOM_PSR_COMM_COMPLETED_ASM 0x1000000000000000 - -/*----------------------------------------------------------------------------+ -| Serial port for CPU2 -+----------------------------------------------------------------------------*/ -#define CPU2_SERIAL_PORT 2 -#define CPU2_BAUD_RATE 115200 - -/*----------------------------------------------------------------------------+ -| External interrupt assignments. -+----------------------------------------------------------------------------*/ -#define EXT_I2C_MASTER 0 -#define EXT_VSP 1 -#define EXT_HT1_BRIDGE 2 -#define EXT_PCI0_AGP_BRIDGE 3 -#define EXT_SLEEP0 4 -#define EXT_SLEEP1 5 -#define EXT_SB_HT0 6 -#define EXT_SB_HT1 7 -#define EXT_SB_HT2 8 -#define EXT_SB_HT3 9 -#define EXT_SB_HT4 10 -#define EXT_SB_HT5 11 -#define EXT_SB_HT6 12 -#define EXT_SB_HT7 13 -#define EXT_SB_HT8 14 -#define EXT_SB_HT9 15 -#define EXT_SB_HT10 16 -#define EXT_SB_HT11 17 -#define EXT_SB_HT12 18 -#define EXT_SB_HT13 19 -#define EXT_SB_HT14 20 -#define EXT_SB_HT15 21 -#define EXT_SB_HT16 22 -#define EXT_SB_HT17 23 -#define EXT_SB_HT18 24 -#define EXT_SB_HT19 25 -#define EXT_SB_HT20 26 -#define EXT_SB_HT21 27 -#define EXT_SB_HT22 28 -#define EXT_SB_HT23 29 -#define EXT_SB_HT24 30 -#define EXT_SB_HT25 31 -#define EXT_SB_HT26 32 -#define EXT_SB_HT27 33 -#define EXT_SB_HT28 34 -#define EXT_SB_HT29 35 -#define EXT_SB_HT30 36 -#define EXT_SB_HT31 37 -#define EXT_SB_HT32 38 -#define EXT_SB_HT33 39 -#define EXT_SB_HT34 40 -#define EXT_SB_HT35 41 -#define EXT_SB_HT36 42 -#define EXT_SB_HT37 43 -#define EXT_SB_HT38 44 -#define EXT_SB_HT39 45 -#define EXT_SB_HT40 46 -#define EXT_SB_HT41 47 -#define EXT_SB_HT42 48 -#define EXT_SB_HT43 49 -#define EXT_SB_HT44 50 -#define EXT_SB_HT45 51 -#define EXT_SB_HT46 52 -#define EXT_SB_HT47 53 -#define EXT_SB_HT48 54 -#define EXT_SB_HT49 55 -#define EXT_SB_HT50 56 -#define EXT_SB_HT51 57 -#define EXT_SB_HT52 58 -#define EXT_SB_HT53 59 -#define EXT_SB_HT54 60 -#define EXT_SB_HT55 61 -#define EXT_SB_HT56 62 -#define EXT_SB_HT57 63 -#define EXT_SB_HT58 64 -#define EXT_SB_HT59 65 -#define EXT_SB_HT60 66 -#define EXT_SB_HT61 67 -#define EXT_SB_HT62 68 -#define EXT_SB_HT63 69 -#define EXT_SB_HT64 70 -#define EXT_SB_HT65 71 -#define EXT_SB_HT66 72 -#define EXT_SB_HT67 73 -#define EXT_SB_HT68 74 -#define EXT_SB_HT69 75 -#define EXT_SB_HT70 76 -#define EXT_SB_HT71 77 -#define EXT_SB_HT72 78 -#define EXT_SB_HT73 79 -#define EXT_SB_HT74 80 -#define EXT_SB_HT75 81 -#define EXT_SB_HT76 82 -#define EXT_SB_HT77 83 -#define EXT_SB_HT78 84 -#define EXT_SB_HT79 85 -#define EXT_SB_HT80 86 -#define EXT_SB_HT81 87 -#define EXT_SB_HT82 88 -#define EXT_SB_HT83 89 -#define EXT_SB_HT84 90 -#define EXT_SB_HT85 91 -#define EXT_SB_HT86 92 -#define EXT_SB_HT87 93 -#define EXT_SB_HT88 94 -#define EXT_SB_HT90 95 -#define EXT_SB_HT91 96 -#define EXT_SB_HT92 97 -#define EXT_SB_HT93 98 -#define EXT_SB_HT94 99 -#define EXT_SB_HT95 100 -#define EXT_SB_HT96 101 -#define EXT_SB_HT97 102 -#define EXT_SB_HT98 103 -#define EXT_SB_HT99 104 -#define EXT_SB_HT100 105 -#define EXT_SB_HT101 106 -#define EXT_SB_HT102 107 -#define EXT_SB_HT103 108 -#define EXT_SB_HT104 109 -#define EXT_SB_HT105 110 -#define EXT_SB_HT106 111 -#define EXT_SB_HT107 112 -#define EXT_SB_HT108 113 -#define EXT_SB_HT109 114 -#define EXT_SB_HT110 115 -#define EXT_SB_HT111 116 -#define EXT_SB_HT112 117 -#define EXT_SB_HT113 118 -#define EXT_SB_HT114 119 -#define EXT_SB_HT115 120 -#define EXT_SB_HT116 121 -#define EXT_SB_HT117 122 -#define EXT_SB_HT118 123 -#define EXT_IPI_0 124 -#define EXT_IPI_1 125 -#define EXT_MAX_IRQ_NUM 125 - -/*----------------------------------------------------------------------------+ -| # # # ###### ####### -| # # # # # # # -| # # # # # # # -| # # # # ###### # -| # # ####### # # # -| # # # # # # # -| ##### # # # # # -+----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------+ -| Interrupt Enable Register. DLAB must be set to 0 access this register. -+----------------------------------------------------------------------------*/ -#define asyncIER 1 -#define asyncIERModem 0x08 -#define asyncIERLine 0x04 -#define asyncIERTransmit 0x02 -#define asyncIERReceive 0x01 -#define asyncIERdisableAll 0x00 - -/*----------------------------------------------------------------------------+ -| Interrupt Identification Register. Read only register. -+----------------------------------------------------------------------------*/ -#define asyncIIR 2 -#define asyncIIRMask 0x0F -#define asyncIIRFifoTimeout 0x0C -#define asyncIIRLine 0x06 -#define asyncIIRReceive 0x04 -#define asyncIIRTransmit 0x02 -#define asyncIIRNoInterrupt 0x01 -#define asyncIIRModem 0x00 - -/*----------------------------------------------------------------------------+ -| FIFO Control Register. Write only register. -+----------------------------------------------------------------------------*/ -#define asyncFCR 2 -#define asyncFCRFifoTrigger14 0xC0 -#define asyncFCRFifoTrigger8 0x80 -#define asyncFCRFifoTrigger4 0x40 -#define asyncFCRFifoTrigger1 0x00 -#define asyncFCRDmaSet 0x08 -#define asyncFCRClearXmitFifo 0x04 -#define asyncFCRClearRcvFifo 0x02 -#define asyncFCRFifoEnable 0x01 - -/*----------------------------------------------------------------------------+ -| Line Control Register. -+----------------------------------------------------------------------------*/ -#define asyncLCR 3 -#define asyncLCRDLAB 0x80 -#define asyncLCRSetBreak 0x40 -#define asyncLCRStickParity 0x20 -#define asyncLCREvenParity 0x10 -#define asyncLCROddParity 0x00 -#define asyncLCRParityEnable 0x08 -#define asyncLCRParityDisable 0x00 -#define asyncLCRStopBitsTwo 0x04 -#define asyncLCRStopBitsOne 0x00 -#define asyncLCRWordLengthSel 0x03 -#define asyncLCRWordLength5 0x00 -#define asyncLCRWordLength6 0x01 -#define asyncLCRWordLength7 0x02 -#define asyncLCRWordLength8 0x03 - -/*----------------------------------------------------------------------------+ -| Modem Control Register. -+----------------------------------------------------------------------------*/ -#define asyncMCR 4 -#define asyncMCRLoop 0x10 -#define asyncMCROut2 0x08 -#define asyncMCROut1 0x04 -#define asyncMCRRTS 0x02 -#define asyncMCRDTR 0x01 -#define asyncMCRdisableAll 0x00 - -/*----------------------------------------------------------------------------+ -| Line Status Register. -+----------------------------------------------------------------------------*/ -#define asyncLSR 5 -#define asyncLSRRxFifoError 0x80 -#define asyncLSRTxEmpty 0x60 -#define asyncLSRTxShiftEmpty 0x40 -#define asyncLSRTxHoldEmpty 0x20 -#define asyncLSRBreakInterrupt 0x10 -#define asyncLSRFramingError 0x08 -#define asyncLSRParityError 0x04 -#define asyncLSROverrunError 0x02 -#define asyncLSRDataReady 0x01 - -/*----------------------------------------------------------------------------+ -| Modem Status Register. Read only register. -+----------------------------------------------------------------------------*/ -#define asyncMSR 6 -#define asyncMSRCD 0x80 -#define asyncMSRRI 0x40 -#define asyncMSRDSR 0x20 -#define asyncMSRCTS 0x10 -#define asyncMSRDeltaDCD 0x08 -#define asyncMSRDeltaRI 0x04 -#define asyncMSRDeltaDSR 0x02 -#define asyncMSRDeltaCTS 0x01 - -/*----------------------------------------------------------------------------+ -| Miscellanies defines. -+----------------------------------------------------------------------------*/ -#define asyncScratchReg 7 -#define asyncTxBuffer 0 -#define asyncRxBuffer 0 -#define asyncDLABLsb 0 -#define asyncDLABMsb 1 - -/*----------------------------------------------------------------------------+ -| ##### ###### ##### ##### ##### ####### -| # # # # # # # # # # # -| # # # # # # # # -| # ###### # ###### ##### ###### -| # # # # # # -| # # # # # # # # # # -| ##### # ##### ##### ####### ##### -+----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------+ -| When performing PCI configuration read/write the configuration address -| register must be written and then read before configuration data register is -| accessed. -| PCI type 0 Configuration address format is: -| 0-20 id. sel., 21-23 function number, 24-29 register number|00 -+----------------------------------------------------------------------------*/ -#define NB_PCI_CONFIGURATION_ADDR 0x0F0800000UL -#define NB_PCI_CONFIGURATION_DATA 0x0F0C00000UL - -/*----------------------------------------------------------------------------+ -| When performing HT configuration read/write the configuration address -| register must be written and then read before configuration data register is -| accessed. -| HT type 0 Configuration address format is: -| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|00 -| HT type 1 configuration address format is -| 0-15 == 0x0000, 16-20 device number, 21-23 function number, 24-29 reg.num|01 -+----------------------------------------------------------------------------*/ -#define NB_HT_CONFIGURATION_ADDR 0x0F2800000UL -#define NB_HT_CONFIGURATION_DATA 0x0F2C00000UL - -/*----------------------------------------------------------------------------+ -| HT Configuration Address Spaces. -+----------------------------------------------------------------------------*/ -#define NB_HT_CONFIG_TYPE_0_BASE 0x0F2000000UL -#define NB_HT_CONFIG_TYPE_1_BASE 0x0F3000000UL - -/*----------------------------------------------------------------------------+ -| HT I/O Space. NB_HT_IO_RESERVED is reserved for Super I/O peripherals. The -| SuperI/O utilizes subtractive decode. All PCI I/0 addresses are translated -| from 0xF4xxxxxx (CPU) to 0x00xxxxxx (PCI). -+----------------------------------------------------------------------------*/ -#define NB_HT_IO_BASE_CPU 0x0F4000000UL -#define NB_HT_IO_BASE_BYTE 0xF4 -#define NB_HT_IO_BASE_BYTE_SH 24 -#define NB_HT_IO_BASE_PCI 0x000000000UL -#define NB_HT_IO_BASE_ASM 0xF4000000 -#define NB_HT_IO_SIZE 0x000400000UL -#define NB_HT_IO_RESERVED 0x000010000UL - -/*----------------------------------------------------------------------------+ -| HT EOI Space. -+----------------------------------------------------------------------------*/ -#define NB_HT_EOI_BASE 0x0F4400000UL -#define NB_HT_EOI_SIZE 0x000400000UL - -/*----------------------------------------------------------------------------+ -| HT Device Header Regs. Big Endian. -+----------------------------------------------------------------------------*/ -#define NB_HT_REG_BASE 0x0F8070000UL -#define NB_HT_DID_VID 0x0F8070000UL -#define NB_HT_STAT_CMD 0x0F8070010UL -#define NB_HT_CLASS_REV 0x0F8070020UL -#define NB_HT_BIST_HT 0x0F8070030UL -#define NB_HT_CAP_PTR 0x0F80700D0UL -#define NB_HT_INT_LINE 0x0F80700F0UL - -/*----------------------------------------------------------------------------+ -| HT Capabilities Block. Big Endian. -+----------------------------------------------------------------------------*/ -#define NB_HT_CMD_PTR_ID 0x0F8070100UL -#define HT_WARM_RESET 0x00010000 -#define NB_HT_LINK_CFG_CONTROL 0x0F8070110UL -#define HT_CRC_ERR 0x00000F00 -#define HT_END_OF_CHAIN 0x00000040 -#define HT_INIT 0x00000020 -#define HT_LINK_FAIL 0x00000010 -#define HT_LINK_OUT_MASK 0x70000000 -#define HT_LINK_IN_MASK 0x07000000 -#define HT_LINK_MAX_OUT_MASK 0x00700000 -#define HT_LINK_MAX_IN_MASK 0x00070000 -#define HT_LINK_WIDTH_8_BIT 0x0 -#define HT_LINK_WIDTH_16_BIT 0x1 -#define HT_LINK_WIDTH_32_BIT 0x3 -#define HT_LINK_WIDTH_2_BIT 0x4 -#define HT_LINK_WIDTH_4_BIT 0x5 -#define NB_HT_LINK_FREQ_ERROR 0x0F8070120UL -#define HT_LINK_FREQ_CAP_MASK 0xFFFF0000 -#define HT_LINK_FREQ_MASK 0x00000F00 -#define HT_LINK_FREQ_200 0x0 -#define HT_LINK_FREQ_300 0x1 -#define HT_LINK_FREQ_400 0x2 -#define HT_LINK_FREQ_500 0x3 -#define HT_LINK_FREQ_600 0x4 -#define HT_LINK_FREQ_800 0x5 -#define HT_LINK_FREQ_1000 0x6 - -/*----------------------------------------------------------------------------+ -| HT Other registers. Big Endian. -+----------------------------------------------------------------------------*/ -#define NB_HT_ADDRESS_MASK 0x0F8070200UL -#define NB_HT_PROCESSOR_INT_CONTROL 0x0F8070210UL -#define NB_HT_BRIDGE_CONTROL 0x0F8070300UL -#define HT_SECBUSRESET 0x00400000 -#define NB_HT_TXCTL_DATABUFALLOC 0x0F8070310UL -#define NB_HT_TXBUFCOUNTMAX 0x0F8070340UL - -/*----------------------------------------------------------------------------+ -| Accessed through AGP/PCI configuration space on PCI0 bus. -+----------------------------------------------------------------------------*/ -#define NB_PCI_ADDRESS_MASK 0x48 -#define NB_PCI_ADDRESS_MASK_RVALUE 0x00000003 - -/*----------------------------------------------------------------------------+ -| MPIC. -+----------------------------------------------------------------------------*/ -#define NB_MPIC_TOGGLE 0x0F80000E0UL -#define NB_MPIC_ENABLE_OUT 0x00000004 -#define NB_MPIC_RESET 0x00000002 - -#define NB_MPIC_BASE 0x0F8040000UL -#define NB_MPIC_SIZE 0x000040000UL - -#define NB_MPIC_FEATURE 0x0F8041000UL -#define NB_MPIC_GLOBAL0 0x0F8041020UL -#define NB_MPIC_GLOBAL0_MPIC_RESET 0x80000000U -#define NB_MPIC_IPI0_VECT_PRIO 0x0F80410A0UL -#define NB_MPIC_IPI1_VECT_PRIO 0x0F80410B0UL -#define NB_MPIC_SPURIOUS_VECTOR 0x0F80410E0UL - -#define NB_MPIC_S0_VECT_PRIO 0x0F8050000UL -#define NB_MPIC_VECT_PRIO_ADDER 0x00000020 -#define NB_MPIC_S0_DESINATION 0x0F8050010UL -#define NB_MPIC_DESINATION_ADDER 0x00000020 - -#define NB_MPIC_P0_IPI0_DISPATCH 0x0F8060040UL -#define NB_MPIC_P0_IPI1_DISPATCH 0x0F8060050UL -#define NB_MPIC_P0_TASK_PRIO 0x0F8060080UL -#define NB_MPIC_P0_INT_ACK 0x0F80600A0UL -#define NB_MPIC_P0_INT_ACK_AS 0x0F80600A0 -#define NB_MPIC_P0_EIO 0x0F80600B0UL -#define NB_MPIC_P0_EIO_AS 0x0F80600B0 -#define NB_MPIC_P1_IPI0_DISPATCH 0x0F8061040UL -#define NB_MPIC_P1_IPI1_DISPATCH 0x0F8061050UL -#define NB_MPIC_P1_TASK_PRIO 0x0F8061080UL -#define NB_MPIC_P1_INT_ACK 0x0F80610A0UL -#define NB_MPIC_P1_INT_ACK_AS 0x0F80610A0 -#define NB_MPIC_P1_EIO 0x0F80610B0UL -#define NB_MPIC_P1_EIO_AS 0x0F80610B0 - -#define NB_MPIC_IPI_PRIO_MASK 0x000F0000 -#define NB_MPIC_IPI_PRIO_SH 16 -#define NB_MPIC_IPI_VECTOR_MASK 0x000000FF -#define NB_MPIC_IPI_MASK 0x80000000U -#define NB_MPIC_IPI_ACTIVE 0x40000000 - -#define NB_MPIC_EXT_PRIO_MASK 0x000F0000 -#define NB_MPIC_EXT_PRIO_SH 16 -#define NB_MPIC_EXT_VECTOR_MASK 0x000000FF -#define NB_MPIC_EXT_MASK 0x80000000U -#define NB_MPIC_EXT_ACTIVE 0x40000000 -#define NB_MPIC_EXT_SENSE 0x00400000 - -#define NB_MPIC_DEST_CPU0 0x00000001 -#define NB_MPIC_DEST_CPU1 0x00000002 - -#define NB_MPIC_IPI_CPU0 0x00000001 -#define NB_MPIC_IPI_CPU1 0x00000002 - -#define NB_MPIC_TASK_PRIO_MASK 0x0000000F - -#define NB_MPIC_C0_CASCADE 0x20000000 - -/*----------------------------------------------------------------------------+ -| I2C. -+----------------------------------------------------------------------------*/ -#define NB_IIC_MMIO_BASE 0xF8001000UL -#define NB_IIC_MMIO_BASE_BYTE4 0xF8 -#define NB_IIC_MMIO_BASE_BYTE5 0x00 -#define NB_IIC_MMIO_BASE_BYTE6 0x10 -#define NB_IIC_MMIO_BASE_BYTE7 0x00 -#define NB_IIC_MMIO_BASE_MASK 0xFFFFFFFF -#define NB_IIC_MMIO_SIZE 0x00001000UL -#define NB_IIC_MODE 0x00 -#define NB_IIC_CNTRL 0x10 -#define NB_IIC_STATUS 0x20 -#define NB_IIC_ISR 0x30 -#define NB_IIC_IER 0x40 -#define NB_IIC_ADDR 0x50 -#define NB_IIC_SUBADDR 0x60 -#define NB_IIC_DATA 0x70 -#define NB_IIC_REV 0x80 -#define NB_IIC_RISETTIMECNT 0x90 -#define NB_IIC_BITTIMECNT 0xA0 - -#define IIC_MODE_PORTSEL0 0x00000000 -#define IIC_MODE_PORTSEL1 0x00000010 -#define IIC_MODE_APMODE_MANUAL 0x00000000 -#define IIC_MODE_APMODE_STANDARD 0x00000004 -#define IIC_MODE_APMODE_SUBADDR 0x00000008 -#define IIC_MODE_APMODE_COMBINED 0x0000000C -#define IIC_MODE_SPEED_25 0x00000002 -#define IIC_MODE_SPEED_50 0x00000001 -#define IIC_MODE_SPEED_100 0x00000000 - -#define IIC_CNTRL_STOP 0x00000004 -#define IIC_CNTRL_XADDR 0x00000002 -#define IIC_CNTRL_AAK 0x00000001 - -#define IIC_STATUS_LASTAAK 0x00000002 - -#define IIC_ISR_ISTOP 0x00000004 -#define IIC_ISR_IADDR 0x00000002 -#define IIC_ISR_IDATA 0x00000001 - -/*----------------------------------------------------------------------------+ -| DDR_SDRAM Controller. -+----------------------------------------------------------------------------*/ -#define NB_SDRAM_BASE 0xF8002000UL -#define NB_SDRAM_BASE_BYTE4 0xF8 -#define NB_SDRAM_BASE_BYTE5 0x00 -#define NB_SDRAM_BASE_BYTE6 0x20 -#define NB_SDRAM_BASE_BYTE7 0x00 -#define NB_SDRAM_BASE_MASK 0xFFFFFFFF -#define NB_SDRAM_SIZE 0x00001000UL -#define NB_SDRAM_MEMTIMINGPARAM 0x050 -#define NB_SDRAM_MEMPROGCNTL 0x0E0 -#define NB_SDRAM_MRS 0x0F0 -#define NB_SDRAM_MRSREGCNTL 0x0F0 -#define NB_SDRAM_EMRS 0x100 -#define NB_SDRAM_EMRSREGCNTL 0x100 -#define NB_SDRAM_MEMBUSCFG 0x190 -#define NB_SDRAM_MEMMODE0 0x1C0 -#define NB_SDRAM_MEMBOUNDAD0 0x1D0 -#define NB_SDRAM_MEMMODE1 0x1E0 -#define NB_SDRAM_MEMBOUNDAD1 0x1F0 -#define NB_SDRAM_MEMMODE2 0x200 -#define NB_SDRAM_MEMBOUNDAD2 0x210 -#define NB_SDRAM_MEMMODE3 0x220 -#define NB_SDRAM_MEMBOUNDAD3 0x230 -#define NB_SDRAM_MEMMODE4 0x240 -#define NB_SDRAM_MEMBOUNDAD4 0x250 -#define NB_SDRAM_MEMMODE5 0x260 -#define NB_SDRAM_MEMBOUNDAD5 0x270 -#define NB_SDRAM_MEMMODE6 0x280 -#define NB_SDRAM_MEMBOUNDAD6 0x290 -#define NB_SDRAM_MEMMODE7 0x2A0 -#define NB_SDRAM_MEMBOUNDAD7 0x2B0 -#define NB_SDRAM_MSCR 0x400 -#define NB_SDRAM_MSRSR 0x410 -#define NB_SDRAM_MSRER 0x420 -#define NB_SDRAM_MSPR 0x430 -#define NB_SDRAM_MCCR 0x440 -#define NB_SDRAM_MESR 0x470 -#define NB_SDRAM_MEMMODECNTL 0x500 -#define NB_SDRAM_DELMEASSTATE 0x510 -#define NB_SDRAM_CKDELADJ 0x520 -#define NB_SDRAM_IOMODECNTL 0x530 -#define NB_SDRAM_DQSDELADJ0 0x600 -#define NB_SDRAM_DQSDATADELADJ0 0x610 - -#define SDRAM_MEMORY_MODE_256M_16Mx16 0x0A000000 -#define SDRAM_MEMORY_MODE_256M_32Mx8 0x0C000000 -#define SDRAM_MEMORY_MODE_512M_64Mx8 0x0E000000 -#define SDRAM_MEMORY_MODE_1G_64Mx16 0x10000000 -#define SDRAM_MEMORY_MODE_1G_128Mx8 0x12000000 - -#define SDRAM_MEMMODE_BANKEN 0x40000000 -#define SDRAM_MEMMODE_BASEBANKADDR 0x01000000 -#define SDRAM_MEMMODE_LSSIDE 0x00800000 -#define SDRAM_MEMMODE_HSSIDE 0x00400000 - -#define SDRAM_MEMBOUNDAD_BASEBANKADDR 0xFF000000 - -#define SDRAM_MEMPROGCNTL_SL 0x80000000 -#define SDRAM_MEMPROGCNTL_WDR 0x40000000 - -#define SDRAM_MTP_RCD_MASK 0xE0000000 -#define SDRAM_MTP_RP_MASK 0x1C000000 -#define SDRAM_MTP_RAS_MASK 0x03800000 -#define SDRAM_MTP_WRT 0x00400000 -#define SDRAM_MTP_RFC_MASK 0x003C0000 -#define SDRAM_MTP_WRCD 0x00020000 -#define SDRAM_MTP_CAS_RR_MASK 0x0001C000 -#define SDRAM_MTP_CAS_RW_MASK 0x00003800 -#define SDRAM_MTP_TRFCX2 0x00000400 - -#define SDRAM_MTP_RCD_2 0x20000000 -#define SDRAM_MTP_RCD_3 0x40000000 -#define SDRAM_MTP_RCD_4 0x60000000 -#define SDRAM_MTP_RCD_5 0x80000000 -#define SDRAM_MTP_RCD_6 0xA0000000 -#define SDRAM_MTP_RP_2 0x04000000 -#define SDRAM_MTP_RP_3 0x08000000 -#define SDRAM_MTP_RP_4 0x0C000000 -#define SDRAM_MTP_RP_5 0x10000000 -#define SDRAM_MTP_RP_6 0x14000000 -#define SDRAM_MTP_RAS_4 0x00000000 -#define SDRAM_MTP_RAS_5 0x00800000 -#define SDRAM_MTP_RAS_6 0x01000000 -#define SDRAM_MTP_RAS_7 0x01800000 -#define SDRAM_MTP_RAS_8 0x02000000 -#define SDRAM_MTP_CAS_RR_2 0x00008000 -#define SDRAM_MTP_CAS_RR_3 0x0000C000 -#define SDRAM_MTP_CAS_RR_4 0x00010000 -#define SDRAM_MTP_CAS_RR_5 0x00014000 -#define SDRAM_MTP_CAS_RR_25 0x00018000 -#define SDRAM_MTP_CAS_RW_2 0x00001000 -#define SDRAM_MTP_CAS_RW_3 0x00001800 -#define SDRAM_MTP_CAS_RW_4 0x00002000 -#define SDRAM_MTP_CAS_RW_5 0x00002800 -#define SDRAM_MTP_CAS_RW_25 0x00003000 - -#define SDRAM_MRS_LTMODE_MASK 0x00000070 -#define SDRAM_MRS_LTMODE_20 0x00000020 -#define SDRAM_MRS_LTMODE_30 0x00000030 -#define SDRAM_MRS_LTMODE_25 0x00000060 -#define SDRAM_MRS_BT 0x00000008 -#define SDRAM_MRS_BL4 0x00000002 - -#define SDRAM_MMCR_REGISTERED_MASK 0x14400000 - -#define SDRAM_MSCR_SCRUBMODOFF 0x00000000 -#define SDRAM_MSCR_SCRUBMODBACKG 0x40000000 -#define SDRAM_MSCR_SCRUBMODIMMED 0x80000000 -#define SDRAM_MSCR_SCRUBMODIMMEDFILL 0xC0000000 -#define SDRAM_MSCR_SI_MASK 0x00FF0000 - -#define SDRAM_MCCR_ECC_EN 0x80000000 -#define SDRAM_MCCR_ECC_APP_DIS 0x40000000 -#define SDRAM_MCCR_EI_EN_H 0x20000000 -#define SDRAM_MCCR_EI_EN_L 0x10000000 -#define SDRAM_MCCR_ECC_UE_MASK_H 0x08000000 -#define SDRAM_MCCR_ECC_CE_MASK_H 0x04000000 -#define SDRAM_MCCR_ECC_UE_MASK_L 0x02000000 -#define SDRAM_MCCR_ECC_CE_MASK_L 0x01000000 -#define SDRAM_MCCR_EI_PAT_H 0x0000FF00 -#define SDRAM_MCCR_EI_PAT_L 0x000000FF - -/*----------------------------------------------------------------------------+ -| Power Management. -+----------------------------------------------------------------------------*/ -#define NB_CLOCK_CTL 0xF8000F00UL -#define HT_LOGIC_STOP_EN 0x00000010 -#define HT_CLK_EN 0x00000008 -#define NB_PLL2 0xF8000F60UL -#define NB_PLL2_BYTE4 0xF8 -#define NB_PLL2_BYTE5 0x00 -#define NB_PLL2_BYTE6 0x0F -#define NB_PLL2_BYTE7 0x60 -#define NB_PLL2_MASK 0xFFFFFFFF -#define PLL2_FORCEPLLLOAD 0x40000000 -#define PLL2_VALUES_MASK 0x0F01F3FF -#define PLL2_266 0x021082B8 -#define PLL2_300 0x021092B8 -#define PLL2_333 0x0210A2B8 -#define PLL2_FEEDBACK_MASK 0x0001F000 -#define PLL2_FEEDBACK_SPEED_266 0x00008000 -#define PLL2_FEEDBACK_SPEED_300 0x00009000 -#define PLL2_FEEDBACK_SPEED_333 0x0000A000 -#define PLL2_FEEDBACK_SPEED_366 0x0000B000 -#define PLL2_FEEDBACK_SPEED_400 0x0000C000 -#define PLL2_FEEDBACK_SPEED_433 0x0000D000 -#define PLL2_FEEDBACK_SPEED_466 0x0000E000 -#define PLL2_FEEDBACK_SPEED_500 0x0000F000 -#define NB_PLL4 0xF8000F80UL -#define PLL4_FORCEPLLLOAD 0x40000000 - -/*----------------------------------------------------------------------------+ -| CPC925 Control. -+----------------------------------------------------------------------------*/ -#define NB_REVISION 0xF8000000UL -#define CPC925_DD1_1 0x00000035 -#define NB_WHOAMI 0xF8000050UL -#define NB_SEMAPHORE 0xF8000060UL -#define NB_HW_INIT_STATE 0xF8000070UL -#define NB_HW_INIT_STATE_ASM 0xF8000070 - -/*----------------------------------------------------------------------------+ -| Processor Interface Registers. -+----------------------------------------------------------------------------*/ -#define NB_PI_APIRDQCFG 0xF8030030UL -#define NB_PI_APIRDQCFG_BYTE4 0xF8 -#define NB_PI_APIRDQCFG_BYTE5 0x03 -#define NB_PI_APIRDQCFG_BYTE6 0x00 -#define NB_PI_APIRDQCFG_BYTE7 0x30 -#define NB_PI_APIRDQCFG_MEMTADLY 0x0000000F -#define NB_PI_APIEXCP 0xF8030060UL -#define NB_PI_APIMASK 0xF8030070UL -#define NB_PI_APIMASK_BYTE4 0xF8 -#define NB_PI_APIMASK_BYTE5 0x03 -#define NB_PI_APIMASK_BYTE6 0x00 -#define NB_PI_APIMASK_BYTE7 0x70 -#define NB_PI_APIMASK_ECC_MASK 0x00F00000 -#define NB_PI_APIMASK_DART 0x80000000 -#define NB_PI_APIMASK_AD0 0x40000000 -#define NB_PI_APIMASK_AD1 0x20000000 -#define NB_PI_APIMASK_STATUS 0x10000000 -#define NB_PI_APIMASK_DATA_ERROR 0x08000000 -#define NB_PI_APIMASK_ADDR0_ERROR 0x04000000 -#define NB_PI_APIMASK_ADDR1_ERROR 0x02000000 - -/*----------------------------------------------------------------------------+ -| DART. -+----------------------------------------------------------------------------*/ -#define NB_DART_BASE 0xF8033000UL -#define NB_DART_SIZE 0x00007000UL - -/*----------------------------------------------------------------------------+ -| ##### # # ###### ####### ###### ### ####### -| # # # # # # # # # # # # -| # # # # # # # # # # # -| ##### # # ###### ##### ###### # # # -| # # # # # # # # # # -| # # # # # # # # # # # -| ##### ##### # ####### # # ####### ### ####### -+----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------+ -| Configuration registers. -+----------------------------------------------------------------------------*/ -#define SUPER_IO_INDEX_OFF 0x2E -#define SUPER_IO_DATA_OFF 0x2F - -#define SUPER_SST_IO_INDEX_OFF 0x2E -#define SUPER_SST_IO_DATA_OFF 0x2F - -#define SUPER_IO_DEVICE_SEL 0x07 -#define SUPER_IO_DEVICE_CONFIG3 0x23 - -#define SUPER_IO_DEVICE_S1 3 -#define SUPER_IO_DEVICE_S2 2 -#define SUPER_IO_DEVICE_SWP 4 -#define SUPER_IO_DEVICE_XBUS 15 -#define SUPER_IO_DEVICE_RTC 16 - -#define SUPER_IO_ADDR_XBUS 0x800 -#define SUPER_IO_ADDR_RTC 0x900 -#define SUPER_IO_ADDR_NVRAM 0x902 -#define SUPER_IO_SWC_BASE 0x700 -#define SUPER_IO_PM_EVT_BASE 0x720 -#define SUPER_IO_PM_CNT_BASE 0x740 -#define SUPER_IO_GPE_BLK_BASE 0x760 -#define SUPER_IO_SWC_LED_CTRL_OFF 0x0A -#define SUPER_IO_SWC_LED_BLINK_OFF 0x0B - -#define SUPER_IO_DEVICE_CTRL 0x30 -#define SUPER_IO_BASE_DEV_MSB 0x60 -#define SUPER_IO_BASE_DEV_LSB 0x61 -#define SUPER_IO_EXT_DEV_MSB 0x62 -#define SUPER_IO_EXT_DEV_LSB 0x63 -#define SUPER_IO_SWP_PM1_CNT_MSB 0x64 -#define SUPER_IO_SWP_PM1_CNT_LSB 0x65 -#define SUPER_IO_SWP_GP1_CNT_MSB 0x66 -#define SUPER_IO_SWP_GP1_CNT_LSB 0x67 -#define SUPER_IO_INT_NUM 0x70 -#define SUPER_IO_INT_TYPE 0x71 -#define SUPER_IO_BASE_NVRAM_SIZE 128 -#define SUPER_IO_EXT_NVRAM_SIZE 128 - -#define SUPER_IO_SERIAL_CONFIG 0xF0 - -#define SUPER_IO_XBUS_CONFIG 0xF8 -#define SUPER_IO_BIOS_SIZE_16M 0x06 -#define SUPER_IO_BIOS_SIZE_1M 0x02 - -#define SUPER_IO_XBUS_XBCNF (SUPER_IO_ADDR_XBUS+ 0x00) -#define SUPER_IO_XBUS_SELECT_MODE0 (SUPER_IO_ADDR_XBUS+ 0x0F) -#define SUPER_IO_XBUS_HOST_ACCESS (SUPER_IO_ADDR_XBUS+ 0x13) - -#define SUPER_IO_XBUS_TRANSPD 0x01 -#define SUPER_IO_TBXCS0 0x10 - -#define SUPER_IO_RTC_DATE_ALARM_OFF 0xF1 -#define SUPER_IO_RTC_MONTH_ALARM_OFF 0xF2 -#define SUPER_IO_RTC_CENTURY_ALARM_OFF 0xF3 - -#define SUPER_IO_RTC_DATE_ALARM_LOC 0x0D -#define SUPER_IO_RTC_MONTH_ALARM_LOC 0x0E -#define SUPER_IO_RTC_CENTURY_ALARM_LOC 0x0F - -#define SUPER_IO_DEVICE_ENABLE 0x01 - -#define SUPER_IO_LED_FUNCTION 0x03 - -#define SUPER_IO_LED_ON_DEF 0x31 -#define SUPER_IO_LED_RATE 0x65 - -#define SUPER_IO_SST_START_CONFIG 0x55 -#define SUPER_IO_SST_STOP_CONFIG 0xAA - -#define SUPER_IO_SST_ID_INDEX 0x20 -#define SUPER_IO_SST_ID_VALUE 0x51 - -#define SUPER_IO_SST_DEVICE_INDEX 0x07 -#define SUPER_IO_SST_DEVICE_S1 0x04 -#define SUPER_IO_SST_DEVICE_S2 0x05 -#define SUPER_IO_SST_DEVICE_RUNTIME 0x0A - -#define SUPER_IO_INT_SELECT 0x70 -#define SUPER_IO_INT_SERIAL_1 0x04 -#define SUPER_IO_INT_SERIAL_2 0x03 - -#define SUPER_IO_SST_RUNTIME_REGS 0x100 - -#define SUPER_IO_BASE_CLOCKL32 0xF0 - -#define SUPER_IO_BASE_CLOCKL32_ALL_OFF 0x03 - -#define SUPER_IO_SST_GPIO_52 0x41 -#define SUPER_IO_SST_GPIO_53 0x42 - -#define SUPER_IO_SST_GPIO_60 0x47 -#define SUPER_IO_SST_GPIO_61 0x48 - -#define SUPER_IO_SST_GPIO_LED1 0x5D -#define SUPER_IO_SST_GPIO_LED2 0x5E - -#define SEPER_IO_SST_RX 0x05 -#define SEPER_IO_SST_TX 0x04 - -#define SEPER_IO_SST_LED1 0x06 -#define SEPER_IO_SST_LED2 0x06 - -#define SEPER_IO_SST_LED_ONE_HZ 0x01 -#define SEPER_IO_SST_LED_HALF_HZ 0x02 - -/*----------------------------------------------------------------------------+ -| # # # ###### ##### # ##### # -| # # ## ## # # # # ## # # ## -| # # # # # # # # # # # # # # # -| # # # # # # # ##### # ##### # -| ####### # # # # # # # # # -| # # # # # # # # # # # # -| # # # # ###### ##### ##### ##### ##### -+----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------+ -| PCI register information. -+----------------------------------------------------------------------------*/ -#define HTT_BRIDGE_ID ((unsigned int)0x7450) -#define HTT_IOAPIC_ID ((unsigned int)0x7451) - -#define HTT_INDEX_OFF 0xB8 -#define HTT_DATA_OFF 0xBC -#define HTT_IOAPIC_CTRL 0x44 -#define HTT_PREF_CONFIG_REG 0x4C -#define HTT_LINK_CFG_A 0xC4 -#define HTT_LINK_CFG_B 0xC8 -#define HTT_LINK_FREQ_CAP_A 0xCC -#define HTT_SEC_STATUS_REG 0xA0 -#define HTT_LINK_FREQ_CAP_B 0xD0 - -/*----------------------------------------------------------------------------+ -| # # # ###### ##### # # # -| # # ## ## # # # # ## ## ## -| # # # # # # # # # # # # # # # # -| # # # # # # # ##### # # # -| ####### # # # # # # # # # -| # # # # # # # # # # # -| # # # # ###### ##### ##### ##### ##### -+----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------+ -| PCI register information. -+----------------------------------------------------------------------------*/ -#define AMD_VENDOR_ID ((unsigned int)0x1022) -#define SB_LPCB_DEV_ID ((unsigned int)0x7468) -#define SB_SYSM_DEV_ID ((unsigned int)0x746B) -#define SB_PCIB_DEV_ID ((unsigned int)0x7460) -#define SB_USB_DEV_ID ((unsigned int)0x7464) -#define SB_EHC_DEV_ID ((unsigned int)0x7463) -#define SB_ENET_DEV_ID ((unsigned int)0x7462) -#define SB_IDE_DEV_ID ((unsigned int)0x7469) -#define SB_SMB_DEV_ID ((unsigned int)0x746A) -#define SB_AC97AUDIO_DEV_ID ((unsigned int)0x746D) -#define SB_AC97MODEM_DEV_ID ((unsigned int)0x746E) - -#define SB_R_IO_CTRL1 0x40 -#define SB_R_LEG_CTRL 0x42 -#define SB_R_ROM_DECODE 0x43 -#define SB_R_MISC_CTRL 0x47 -#define SB_R_FUNC_ENABLE 0x48 -#define SB_R_IOAPIC_C0 0x4A -#define SB_R_IOAPIC_C1 0x4B -#define SB_R_SCICONFIG 0x42 -#define SB_R_PNP_IRQ_SEL 0x44 -#define SB_R_SERIRQ_CONNF 0x4A -#define SB_R_PCI_PREF_C0 0x50 -#define SB_R_PCI_PREF_C1 0x54 -#define SB_R_PCI_IRQ_ROUTE 0x56 -#define SB_R_NVCTRL 0x74 - -#define SB_LPC_ROM_W 0x01 -#define SB_LPC_ROM_SIZE 0xC0 -#define SB_PCI_PR_C0 0x00000000 -#define SB_PCI_PR_C1 0x0000718D -#define SB_NVRAM_EN 0xDE01 - -#define SB_SYSM_CC_WRITE 0x60 - -#define SB_NVRAM_ADDR (NB_HT_IO_BASE_CPU+ 0xDE00) -#define SB_NVRAM_SIZE 0x100 - -/*----------------------------------------------------------------------------+ -| IDE controller -+----------------------------------------------------------------------------*/ -#define SB_IDE_PRI_BASE (NB_HT_IO_BASE_CPU+ 0x1F0) -#define SB_IDE_SEC_BASE (NB_HT_IO_BASE_CPU+ 0x170) - -#define IDE_RANGE_LEGACY 0xCC00 - -#define SB_EIDEC_CMD 0x04 -#define SB_EIDEC_PROG 0x08 -#define SB_EIDEC_INT 0x3C -#define SB_EIDEC_CONFIG 0x40 - -#define EIDEC_CMD_BMEN 0x00000004 -#define EIDEC_CMD_IOEN 0x00000001 -#define EIDEC_PROG_PROGIF2 0x00000400 -#define EIDEC_PROG_PROGIF0 0x00000100 -#define EIDEC_CONFIG_PRIEN 0x00000002 -#define EIDEC_CONFIG_SECEN 0x00000001 - -/*----------------------------------------------------------------------------+ -| LPC bus. -+----------------------------------------------------------------------------*/ -#define SB_LPC_FUNCENAB 0x48 -#define LPC_FUNCENAB_IDE 0x0002 - -#define SB_RTC_LEG_ADDR 0x70 -#define SB_RTC_LEG_DATA 0x71 - -/*----------------------------------------------------------------------------+ -| RTC. -+----------------------------------------------------------------------------*/ -#define SB_RTC_ADDR_PORT70 (NB_HT_IO_BASE_CPU+ 0x70) -#define SB_RTC_DATA_PORT71 (NB_HT_IO_BASE_CPU+ 0x71) -#define SB_RTC_ADDR_PORT72 (NB_HT_IO_BASE_CPU+ 0x72) -#define SB_RTC_DATA_PORT73 (NB_HT_IO_BASE_CPU+ 0x73) - -#ifdef __cplusplus -} -#endif - -#endif /* _PPC970FX_H_ */ diff --git a/src/mainboard/momentum/apache/timerspeed.S b/src/mainboard/momentum/apache/timerspeed.S new file mode 100755 index 0000000000..483a2aa344 --- /dev/null +++ b/src/mainboard/momentum/apache/timerspeed.S @@ -0,0 +1,378 @@ +#include + +/*----------------------------------------------------------------------------+ +| Cycle counts ((1/ 9600)* 10) / (1/speed)) - 2%. ++----------------------------------------------------------------------------*/ +#define SPEED_6_25 (0x0000196E- (65* 2)) +#define SPEED_7_159 (0x00001D21- (74* 2)) +#define SPEED_8_33 (0x000021E5- (86* 2)) +#define SPEED_10_4 (0x00002A51- (108* 2)) +#define SPEED_14_318 (0x00003A42- (149* 2)) +#define SPEED_16_66 (0x000043D0- (173* 2)) +#define SPEED_25 (0x000065B9- (260* 2)) +#define SPEED_33 (0x000087A2- (347* 2)) +#define SPEED_40 (0x0000A2C2- (416* 2)) +#define SPEED_50 (0x0000CB73- (520* 2)) +#define SPEED_66 (0x00010C8E- (687* 2)) +#define SPEED_80 (0x00014585- (833* 2)) +#define SPEED_100 (0x000196E6- (1041* 2)) +#define SPEED_125 (0x0001FCA0- (1302* 2)) +#define SPEED_133 (0x00021D2D- (1385* 2)) +#define SPEED_150 (0x0002625A- (1562* 2)) +#define SPEED_166 (0x0002A374- (1729* 2)) +#define SPEED_175 (0x0002C813- (1822* 2)) +#define SPEED_200 (0x00032DCD- (2093* 2)) +#define SPEED_225 (0x00039387- (2343* 2)) +#define SPEED_250 (0x0003F940- (2604* 2)) +#define SPEED_275 (0x00045EFA- (2864* 2)) +#define SPEED_300 (0x0004C4B4- (3125* 2)) +#define SPEED_3375 (0x00055D4A- (3515* 2)) +#define SPEED_375 (0x0005F5E1- (3906* 2)) +#define SPEED_400 (0x00065B9A- (4166* 2)) +#define SPEED_433 (0x0006E1E1- (4510* 2)) +#define SPEED_466 (0x00076828- (4854* 2)) +#define SPEED_500 (0x0007F281- (5208* 2)) + +/*----------------------------------------------------------------------------+ +| Timebase_speed_calc ++----------------------------------------------------------------------------*/ + function_prolog(timebase_speed_calc) + mfmsr r10 + rlwinm r11,r10,0,17,15 + mtmsrd r11,1 + isync + /*--------------------------------------------------------------------+ + | Make sure that all the characters in the transmit buffer are sent. + +--------------------------------------------------------------------*/ +..sent: lbz r6,asyncLSR(r3) + andi. r6,r6,0x0060 + cmpi cr0,1,r6,0x0060 + bne ..sent + /*--------------------------------------------------------------------+ + | Store current serial port settings in r11, r12. + | r11 BH (baud high), BL (baud low), LCR + | r12 MCR, IER, FCR + +--------------------------------------------------------------------*/ + lbz r4,asyncLCR(r3) + ori r11,r4,0x0000 + lbz r4,asyncFCR(r3) + ori r12,r4,0x0000 + lbz r4,asyncIER(r3) + rlwimi r12,r4,8,16,23 + lbz r4,asyncMCR(r3) + rlwimi r12,r4,16,8,15 + /*--------------------------------------------------------------------+ + | Store BH and BL and program new baud rate. + +--------------------------------------------------------------------*/ + addi r4,r0,0x80 + stb r4,asyncLCR(r3) + lbz r4,asyncDLABMsb(r3) + rlwimi r11,r4,16,8,15 + addi r4,r0,DIV_HIGH_9600 + stb r4,asyncDLABMsb(r3) + lbz r4,asyncDLABLsb(r3) + rlwimi r11,r4,8,16,23 + addi r4,r0,DIV_LOW_9600 + stb r4,asyncDLABLsb(r3) + addi r4,r0,0x03 + stb r4,asyncLCR(r3) + /*--------------------------------------------------------------------+ + | Put the serial port in loop-back mode. + +--------------------------------------------------------------------*/ + addi r4,r0,0x00 + stb r4,asyncFCR(r3) + stb r4,asyncIER(r3) + addi r4,r0,0x10 + stb r4,asyncMCR(r3) + lbz r4,asyncRxBuffer(r3) + addi r4,r0,0x0041 + /*--------------------------------------------------------------------+ + | Again make sure there are no characters in transmit buffer. + +--------------------------------------------------------------------*/ + addi r5,r0,0 +..again:lbz r6,asyncLSR(r3) + andi. r6,r6,0x0060 + cmpi cr0,1,r6,0x0060 + bne ..again + /*--------------------------------------------------------------------+ + | Take a snapshot of the timebase. + +--------------------------------------------------------------------*/ + mfspr r7,tblr + /*--------------------------------------------------------------------+ + | Send a character while in loopback mode. This will be done twice. + | Once to get the instuctions into I-cache, the second time for the + | real measurement. + +--------------------------------------------------------------------*/ + stb r4,asyncTxBuffer(r3) +..spnlp:lbz r6,asyncLSR(r3) + andi. r6,r6,0x01 + beq ..spnlp + mfspr r9,tblr + /*--------------------------------------------------------------------+ + | Perform subtraction to determine how many timebase ticks it took + | to transmit the character. + +--------------------------------------------------------------------*/ + subfc r9,r7,r9 + /*--------------------------------------------------------------------+ + | Consume the character sent in loopback mode. + +--------------------------------------------------------------------*/ + lbz r4,asyncRxBuffer(r3) + eieio + /*--------------------------------------------------------------------+ + | If the first character was just sent, go back and send a second. + +--------------------------------------------------------------------*/ + cmpi cr0,1,r5,0x0000 + addi r5,r5,1 + beq ..again + /*--------------------------------------------------------------------+ + | Restore serial port settings. + +--------------------------------------------------------------------*/ + addi r4,r0,0x80 + stb r4,asyncLCR(r3) + rlwinm r4,r11,16,24,31 + stb r4,asyncDLABMsb(r3) + rlwinm r4,r11,24,24,31 + stb r4,asyncDLABLsb(r3) + rlwinm r4,r11,0,24,31 + stb r4,asyncLCR(r3) + rlwinm r4,r12,16,24,31 + stb r4,asyncMCR(r3) + rlwinm r4,r12,24,24,31 + stb r4,asyncIER(r3) + rlwinm r4,r12,0,24,31 + stb r4,asyncFCR(r3) + /*--------------------------------------------------------------------+ + | Calculate timebase speed (r9 is the time we are referencing). + +--------------------------------------------------------------------*/ + addis r4,r0,SPEED_7_159@h + ori r4,r4,SPEED_7_159@l + cmp cr0,r9,r4 + blt ..freq6 + addis r4,r0,SPEED_8_33@h + ori r4,r4,SPEED_8_33@l + cmp cr0,r9,r4 + blt ..freq7 + addis r4,r0,SPEED_10_4@h + ori r4,r4,SPEED_10_4@l + cmp cr0,r9,r4 + blt ..freq8 + addis r4,r0,SPEED_14_318@h + ori r4,r4,SPEED_14_318@l + cmp cr0,r9,r4 + blt ..freq10 + addis r4,r0,SPEED_16_66@h + ori r4,r4,SPEED_16_66@l + cmp cr0,r9,r4 + blt ..freq14 + addis r4,r0,SPEED_25@h + ori r4,r4,SPEED_25@l + cmp cr0,r9,r4 + blt ..freq16 + addis r4,r0,SPEED_33@h + ori r4,r4,SPEED_33@l + cmp cr0,r9,r4 + blt ..freq25 + addis r4,r0,SPEED_40@h + ori r4,r4,SPEED_40@l + cmp cr0,r9,r4 + blt ..freq33 + addis r4,r0,SPEED_50@h + ori r4,r4,SPEED_50@l + cmp cr0,r9,r4 + blt ..freq40 + addis r4,r0,SPEED_66@h + ori r4,r4,SPEED_66@l + cmp cr0,r9,r4 + blt ..freq50 + addis r4,r0,SPEED_80@h + ori r4,r4,SPEED_80@l + cmp cr0,r9,r4 + blt ..freq66 + addis r4,r0,SPEED_100@h + ori r4,r4,SPEED_100@l + cmp cr0,r9,r4 + blt ..freq80 + addis r4,r0,SPEED_125@h + ori r4,r4,SPEED_125@l + cmp cr0,r9,r4 + blt ..freq100 + addis r4,r0,SPEED_133@h + ori r4,r4,SPEED_133@l + cmp cr0,r9,r4 + blt ..freq125 + addis r4,r0,SPEED_150@h + ori r4,r4,SPEED_150@l + cmp cr0,r9,r4 + blt ..freq133 + addis r4,r0,SPEED_166@h + ori r4,r4,SPEED_166@l + cmp cr0,r9,r4 + blt ..freq150 + addis r4,r0,SPEED_175@h + ori r4,r4,SPEED_175@l + cmp cr0,r9,r4 + blt ..freq166 + addis r4,r0,SPEED_200@h + ori r4,r4,SPEED_200@l + cmp cr0,r9,r4 + blt ..freq175 + addis r4,r0,SPEED_225@h + ori r4,r4,SPEED_225@l + cmp cr0,r9,r4 + blt ..freq200 + addis r4,r0,SPEED_250@h + ori r4,r4,SPEED_250@l + cmp cr0,r9,r4 + blt ..freq225 + addis r4,r0,SPEED_275@h + ori r4,r4,SPEED_275@l + cmp cr0,r9,r4 + blt ..freq250 + addis r4,r0,SPEED_300@h + ori r4,r4,SPEED_300@l + cmp cr0,r9,r4 + blt ..freq275 + addis r4,r0,SPEED_3375@h + ori r4,r4,SPEED_3375@l + cmp cr0,r9,r4 + blt ..freq300 + addis r4,r0,SPEED_375@h + ori r4,r4,SPEED_375@l + cmp cr0,r9,r4 + blt ..freq3375 + addis r4,r0,SPEED_400@h + ori r4,r4,SPEED_400@l + cmp cr0,r9,r4 + blt ..freq375 + addis r4,r0,SPEED_433@h + ori r4,r4,SPEED_433@l + cmp cr0,r9,r4 + blt ..freq400 + addis r4,r0,SPEED_466@h + ori r4,r4,SPEED_466@l + cmp cr0,r9,r4 + blt ..freq433 + addis r4,r0,SPEED_500@h + ori r4,r4,SPEED_500@l + cmp cr0,r9,r4 + blt ..freq466 + b ..freq500 +..freq6: + addis r3,r0,0x005F + ori r3,r3,0x5e10 + b ..end +..freq7: + addis r3,r0,0x006D + ori r3,r3,0x3CD8 + b ..end +..freq8: + addis r3,r0,0x007F + ori r3,r3,0x2815 + b ..end +..freq10: + addis r3,r0,0x009e + ori r3,r3,0xb100 + b ..end +..freq14: + addis r3,r0,0x00da + ori r3,r3,0x79b0 + b ..end +..freq16: + addis r3,r0,0x00fe + ori r3,r3,0x502A + b ..end +..freq25: + addis r3,r0,0x017D + ori r3,r3,0x7840 + b ..end +..freq33: + addis r3,r0,0x01FC + ori r3,r3,0xA055 + b ..end +..freq40: + addis r3,r0,0x0262 + ori r3,r3,0x5A00 + b ..end +..freq50: + addis r3,r0,0x02FA + ori r3,r3,0xF080 + b ..end +..freq66: + addis r3,r0,0x03F9 + ori r3,r3,0x40AA + b ..end +..freq80: + addis r3,r0,0x04C4 + ori r3,r3,0xB400 + b ..end +..freq100: + addis r3,r0,0x05F5 + ori r3,r3,0xE100 + b ..end +..freq125: + addis r3,r0,0x0773 + ori r3,r3,0x5940 + b ..end +..freq133: + addis r3,r0,0x07F2 + ori r3,r3,0x8155 + b ..end +..freq150: + addis r3,r0,0x08F0 + ori r3,r3,0xD180 + b ..end +..freq166: + addis r3,r0,0x09EF + ori r3,r3,0x21AA + b ..end +..freq175: + addis r3,r0,0x0A6E + ori r3,r3,0x49C0 + b ..end +..freq200: + addis r3,r0,0x0BEB + ori r3,r3,0xC200 + b ..end +..freq225: + addis r3,r0,0x0D69 + ori r3,r3,0x3A40 + b ..end +..freq250: + addis r3,r0,0x0EE6 + ori r3,r3,0xB280 + b ..end +..freq275: + addis r3,r0,0x1064 + ori r3,r3,0x2AC0 + b ..end +..freq300: + addis r3,r0,0x11E1 + ori r3,r3,0xA300 + b ..end +..freq3375: + addis r3,r0,0x141D + ori r3,r3,0xD760 + b ..end +..freq375: + addis r3,r0,0x165A + ori r3,r3,0x0BC0 + b ..end +..freq400: + addis r3,r0,0x17D7 + ori r3,r3,0x8400 + b ..end +..freq433: + addis r3,r0,0x19CF + ori r3,r3,0x0E40 + b ..end +..freq466: + addis r3,r0,0x1BC6 + ori r3,r3,0x9880 + b ..end +..freq500: + addis r3,r0,0x1DCD + ori r3,r3,0x6500 +..end: mtmsrd r10,1 + isync + blr + function_epilog(timebase_speed_calc) diff --git a/src/northbridge/ibm/cpc925/Config.lb b/src/northbridge/ibm/cpc925/Config.lb index 8559c2e66a..f57ce0a075 100644 --- a/src/northbridge/ibm/cpc925/Config.lb +++ b/src/northbridge/ibm/cpc925/Config.lb @@ -6,7 +6,9 @@ config chip.h initobject cpc925.o initobject cpc925_pci.o +initobject cpc925_sdram.o object cpc925.o object cpc925_pci.o +object cpc925_sdram.o driver cpc925_northbridge.o diff --git a/src/northbridge/ibm/cpc925/cpc925_sdram.c b/src/northbridge/ibm/cpc925/cpc925_sdram.c new file mode 100644 index 0000000000..1347adb6c2 --- /dev/null +++ b/src/northbridge/ibm/cpc925/cpc925_sdram.c @@ -0,0 +1,13 @@ +#include "ppc970.h" + +unsigned long sdram_size(void) +{ + unsigned long addr1, addr2; + + addr1=inint(NB_SDRAM_BASE+NB_SDRAM_MEMMODE7)&SDRAM_MEMMODE_BASEBANKADDR; + addr1=addr1<<11; + addr2=inint(NB_SDRAM_BASE+NB_SDRAM_MEMBOUNDAD7)&SDRAM_MEMBOUNDAD_BASEBANKADDR; + addr2=addr2<<3; + return(addr1|addr2); + +} -- cgit v1.2.3