From f11b81d18d36ecf732452a861d79ecd75f380adc Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 1 Oct 2010 12:24:57 +0000 Subject: fix VIA C7 code. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/via/car/cache_as_ram.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 6389a3833f..6bd2c0f393 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -100,7 +100,8 @@ clear_fixed_var_mtrr_out: */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(1), %ecx @@ -243,7 +244,8 @@ testok: /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ movl $MTRRphysBase_MSR(3), %ecx xorl %edx, %edx - movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr movl $MTRRphysMask_MSR(3), %ecx -- cgit v1.2.3