From f47c4bcd01ffb1c1279eb94481ca0143608a0983 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 30 Jul 2013 15:43:43 -0700 Subject: slippy/falco/peppy: Route USB to XHCI on resume Turn on the pei_data flag that will instruct the reference code binary to route all USB ports to the XHCI controller on resume and disable the EHCI controller(s). Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/63798 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4404 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/falco/romstage.c | 1 + src/mainboard/google/peppy/romstage.c | 1 + src/mainboard/google/slippy/romstage.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index fcf06a918b..0ad4b9763f 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist) // Enable 2x refresh mode ddr_refresh_2x: 1, max_ddr3_freq: 1600, + usb_xhci_on_resume: 1, usb2_ports: { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: Port A, CN8 */ diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index abc082c8eb..c6696c09f6 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -143,6 +143,7 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, max_ddr3_freq: 1600, + usb_xhci_on_resume: 1, usb2_ports: { /* Length, Enable, OCn#, Location */ { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index a93196a95b..fdbac97695 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -158,6 +158,7 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, max_ddr3_freq: 1600, + usb_xhci_on_resume: 1, usb2_ports: { /* Length, Enable, OCn#, Location */ { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */ -- cgit v1.2.3