From f6004114ec3807e15acbc01cee45d4f83254bae2 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Mon, 17 May 2021 12:25:40 +0530 Subject: intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask definition Definition for NAV_FWE BIT was added in commit e6e8b3d Even if try to set this BIT it was not getting set since PAD_CFG_DW0 mask will make it 0 since this bit was not part of mask. Adding NAV_FWE to mask will resolve this issue and BIT will be set/unset as per programming in mainboard. TEST=Check GPIO register dump and see if BIT is getting set properly. Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/54350 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/gpio/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 8dc92ffb34..8f1c3a5601 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -24,7 +24,7 @@ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \ - PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \ + PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | PAD_CFG0_NAFVWE_ENABLE |\ PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) -- cgit v1.2.3