From f9650771d3cb7e0244ef6caa5b7f7c67d5425a40 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 24 Mar 2021 16:49:14 +0530 Subject: mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PM This patch allows overriding GPIO PM miscconfig register for each GPIO community to avoid dynamic clock gating. TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0] are set to '0'. Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/intel/adlrvp/devicetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index f78fe2c3ee..cade987313 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -40,6 +40,16 @@ chip soc/intel/alderlake register "gen3_dec" = "0x00fc0901" register "gen4_dec" = "0x000c0081" + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 2 -- cgit v1.2.3