From ffa520fc13da3504efb2e9a8d50f5fbd91580a09 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 7 Jan 2020 12:00:31 +0200 Subject: intel/sandybridge,bd82x6x: Move enable_smbus() call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/38298 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/romstage.c | 3 --- src/southbridge/intel/bd82x6x/early_pch.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 079e1b13ba..7d1c019207 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -82,9 +82,6 @@ void mainboard_romstage_entry(void) mainboard_early_init(s3resume); - /* Enable SPD ROMs and DDR-III DRAM */ - enable_smbus(); - post_code(0x39); perform_raminit(s3resume); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index b19216b9ec..6f06a57129 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -327,4 +327,7 @@ void early_pch_init(void) pch_enable_gbe(); setup_pch_gpios(&mainboard_gpio_map); + + if (ENV_ROMSTAGE) + enable_smbus(); } -- cgit v1.2.3