From c1e4f8995362c6eb7d09dfc0618edcc636d30acc Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 7 Jan 2016 11:24:24 -0800 Subject: Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/SoC/soc.html | 105 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/Intel/SoC/soc.html (limited to 'Documentation/Intel/SoC/soc.html') diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html new file mode 100644 index 0000000000..30821dcd9c --- /dev/null +++ b/Documentation/Intel/SoC/soc.html @@ -0,0 +1,105 @@ + + + + SoC + + + +

x86 System on a Chip (SoC) Development

+

+ SoC development is best done in parallel with development for a specific + board. The combined steps are listed + here. + The development steps for the SoC are listed below: +

+
    +
  1. FSP 1.1 required files
    2. +
  2. SoC Required Files
    3. +
  3. Start Booting
    4. +
  4. Early Debug
    5. +
+ + +
+

Required Files

+

+ Create the directory as src/soc/<Vendor>/<Chip Family>. +

+ +

+ The following files are required to build a new SoC: +

+
    +
  • Include files +
      +
    • include/soc/pei_data.h
      • +
    • include/soc/pm.h
      • +
    +
    • +
  • Kconfig - Defines the Kconfig value for the SoC and selects the tool + chains for the various stages: +
      +
    • select ARCH_BOOTBLOCK_<Tool Chain>
      • +
    • select ARCH_RAMSTAGE_<Tool Chain>
      • +
    • select ARCH_ROMSTAGE_<Tool Chain>
      • +
    • select ARCH_VERSTAGE_<Tool Chain>
      • +
    +
    • +
  • Makefile.inc - Specify the include paths
    • +
  • memmap.c - Top of usable RAM
    • +
+ + +
+

Start Booting

+

+ Some SoC parts require additional firmware components in the flash. + This section describes how to add those pieces. +

+ +

Intel Firmware Descriptor

+

+ The Intel Firmware Descriptor (IFD) is located at the base of the flash part. + The following command overwrites the base of the flash image with the Intel + Firmware Descriptor: +

+
dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1
+ + +

Management Engine Binary

+

+ Some SoC parts contain and require that the Management Engine (ME) be running + before it is possible to bring the x86 processor out of reset. A binary file + containing the management engine code must be added to the firmware using the + ifdtool. The following commands add this binary blob: +

+
util/ifdtool/ifdtool -i ME:me.bin  build/coreboot.rom
+mv build/coreboot.rom.new build/coreboot.rom
+
+ + +

Early Debug

+

+ Early debugging between the reset vector and the time the serial port is enabled + is most easily done by writing values to port 0x80. +

+ + +

Success

+

+ When the reset vector is successfully invoked, port 0x80 will output the following value: +

+ + + +
+

Modified: 31 January 2016

+ + \ No newline at end of file -- cgit v1.2.3