From 55069d15d8a6dcd7f8eaaf36e85e5d7a53fdaae6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 1 Nov 2019 21:53:36 +0100 Subject: arch/riscv: Pass cbmem_top to ramstage via calling argument Tested on the Qemu-Virt target both 32 and 64 bit. Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- Documentation/arch/riscv/index.md | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/arch/riscv/index.md') diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md index ea6a5cd47e..e0d37f591c 100644 --- a/Documentation/arch/riscv/index.md +++ b/Documentation/arch/riscv/index.md @@ -19,6 +19,9 @@ On entry to a stage or payload (including SELF payloads), * all harts are running. * A0 is the hart ID. * A1 is the pointer to the Flattened Device Tree (FDT). +* A2 contains the additional program calling argument: + - cbmem_top for ramstage + - the address of the payload for opensbi ## Additional payload handoff requirements The location of cbmem should be placed in a node in the FDT. -- cgit v1.2.3