From 84bf089f6a769a88db9717787eab078b00aaafb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sun, 28 Oct 2018 02:48:25 +0200 Subject: Documentation/mainboard: Add emulation/spike-riscv.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Philipp Hug --- Documentation/mainboard/emulation/spike-riscv.md | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/mainboard/emulation/spike-riscv.md (limited to 'Documentation/mainboard/emulation/spike-riscv.md') diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md new file mode 100644 index 0000000000..55e87d9cc9 --- /dev/null +++ b/Documentation/mainboard/emulation/spike-riscv.md @@ -0,0 +1,23 @@ +# Spike RISC-V emulator + +[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator. + + +## Installation + +- Download `riscv-fesvr` and `riscv-isa-sim` from +- Apply the two patches in , + which are necessary in order to have a serial console +- Compile `riscv-fesvr` and then `riscv-isa-sim` + + +## Building coreboot and running it in Spike + +- Configure coreboot and run `make` as usual +- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to + convert coreboot to an ELF that Spike can load +- Run `spike -m1024 build/coreboot.elf` + + +[Spike]: https://github.com/riscv/riscv-isa-sim +[RISC-V]: https://riscv.org/ -- cgit v1.2.3