From 5a1ba1bc291e1db409ee302762222095fc24deff Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 19 Dec 2019 10:57:33 -0700 Subject: Documentation/soc/amd: Add PSP integration information Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- Documentation/soc/amd/family17h.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'Documentation/soc/amd/family17h.md') diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index dc3de13ffe..9608b57325 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -18,8 +18,8 @@ To the extent necessary, the role of the Platform Security Processor (a.k.a. PSP) in system initialization is addressed here. AMD has historically required an NDA for access to the PSP specification1. coreboot relies on util/amdfwtool to build -the structures and add various other firmware to the final image. The -Family 17h PSP design guide adds a new BIOS Directory Table, similar to +the structures and add various other firmware to the final image2. +The Family 17h PSP design guide adds a new BIOS Directory Table, similar to the PSP Directory Table. Support in coreboot for modern AMD products is based on AMD’s @@ -29,12 +29,12 @@ configuring proprietary core logic, assistance with generating ACPI tables, and other features. AGESA for products earlier than Family 17h is known as v5 or -Arch20082. Also note that coreboot currently contains both +Arch20083. Also note that coreboot currently contains both open source AGESA and closed source implementations (binaryPI) compiled from AGESA. The first AMD Family 17h device ported to coreboot is codenamed -“Picasso”3, and will be added to soc/amd/picasso. +“Picasso”4, and will be added to soc/amd/picasso. ## Additional Definitions @@ -207,7 +207,7 @@ the existing v5 interface impractical. Given the UEFI nature of modern AGESA, and the existing open source work from Intel, Picasso shall support AGESA via an FSP-like prebuilt -image. The Intel Firmware Support Package4 combines +image. The Intel Firmware Support Package5 combines reference code with EDK II source to create a modular image with discoverable entry points. coreboot source already contains knowledge of FSP, how to parse it, integrate it, and how to communicate with it. @@ -218,7 +218,7 @@ of FSP, how to parse it, integrate it, and how to communicate with it. for AMD Family 17h Processors” (PID #55758) and “AMD Platform Security Processor BIOS Architecture Design Guide” (PID #54267) for earlier products -2. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf) -3. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso) -4. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html) - +2. [PSP Integration](psp_integration.md) +3. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf) +4. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso) +5. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html) -- cgit v1.2.3