From 07eb01bc02ac121fb0a208c8f6a53a8123691c93 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 7 May 2021 21:23:21 +0200 Subject: doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Felix Held Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53924 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- Documentation/releases/coreboot-4.14-relnotes.md | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation') diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md index e383c2edc4..6b629f476a 100644 --- a/Documentation/releases/coreboot-4.14-relnotes.md +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -52,4 +52,13 @@ scenarios. Significant changes ------------------- +### AMD SoC cleanup and initial Cezanne APU support + +There's initial support for the AMD Cezanne APUs in the tree. This code +hasn't started as a copy of the previous generation, but was based on a +slightly modified version of the example/min86 SoC. During the cleanup +of the existing Picasso SoC code the common parts of the code were +moved to the common AMD SoC code, so that they could be used by the +Cezanne code instead of adding another slightly different copy. + ### Add significant changes here -- cgit v1.2.3