From 24302633a558e545efcc84178136bd1879f6d8ee Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 16 May 2019 14:08:31 -0600 Subject: post_code: add post code for memory error Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails to initialize RAM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533 Signed-off-by: Keith Short Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- Documentation/POSTCODES | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES index 855940f433..2a8285b27f 100644 --- a/Documentation/POSTCODES +++ b/Documentation/POSTCODES @@ -19,6 +19,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4. 0xe0 Boot media (e.g. SPI ROM) is corrupt 0xe1 Resource stored within CBFS is corrupt 0xe2 Vendor binary (e.g. FSP) generated a fatal error +0xe3 RAM could not be initialized 0xf8 Entry into elf boot 0xf3 Jumping to payload -- cgit v1.2.3