From 2d96be6484217bf070a1f0e8270661dc355033d6 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Tue, 17 May 2016 17:03:00 -0700 Subject: Documentation/Intel: Update the documentation index.html: * Separate the sections on the main page * Move the documentation links to the main page * Add links for FSP 1.0 and 2.0 specifications * Add link for UEFI specifications * Add link to MinnowBoard MAX coreboot fsp1_1.html: * Use Integration instead of Documentation SoC/quark.html: * Move documentation to main page * Update build instructions for CorebootPayloadPkg * Remove FatPkg since it is now part of edk2 tree * Add source location for QuarkFspPkg * Add build instructions for QuarkFspPkg TEST=None Change-Id: I48bd1bf98a6d8bc43bdd3b4c51dfd119a1e0f61b Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/14882 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- Documentation/Intel/SoC/quark.html | 104 +++++++++++-------------------------- Documentation/Intel/fsp1_1.html | 8 +-- Documentation/Intel/index.html | 37 +++++++++++-- 3 files changed, 68 insertions(+), 81 deletions(-) (limited to 'Documentation') diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index 5f5da72d89..61abebd239 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -18,6 +18,8 @@
  • SoC support
  • FSP 1.1 integration
  • Board support
    • +
  • Quark™ FSP
    • +
  • CorebootPayloadPkg
    • @@ -29,7 +31,6 @@

    Quark™ Documentation

    @@ -53,56 +55,18 @@ Build Instructions:

    1. Set up build environment
      2. -
    2. For the Galileo Gen 2, replace the following lines in - CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc: -
        gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8
-
      -with: -
      #
-# Quark configuration
-#
-  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|1
-
-#
-# Specify Galileo HSUART1 serial port
-#
-[PcdsPatchableInModule.common]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0xff}
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xA0019000
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4
-
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|44236800
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|3 # 8-bits, no parity
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|1 # Enable FIFO
-  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|16
-
      -
      3. -
    3. Build Instructions: -
        -
      • Linux (assumes GCC48): -
          -
        1. Edit Conf/tools_def.txt to add " -march=i586" to the IA32_CC_FLAGS - for the GCC compiler being used: -
          *_GCC48_IA32_CC_FLAGS             = DEF(GCC48_IA32_CC_FLAGS) -Os -march=i586
          -
          2. -
        2. -
          build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc  -a IA32  -t GCC48  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
+  
        3. Linux (assumes GCC48):
+
          build  -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc  -a IA32  \
+    -t GCC48  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  \
+    -DDEBUG_PRINT_ERROR_LEVEL=0x80000042  -DSHELL_TYPE=BUILD_SHELL  \
+    -DMAX_LOGICAL_PROCESSORS=1
 ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd
 
          
-          
          4. 
-
        -
        • -
      • Windows: -
        build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc  -a IA32  -t VS2012x86  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
-dir Build\CorebootPayloadPkgIA32\DEBUG_VS2012x86\FV\UEFIPAYLOAD.fd
+
        • +
      • Windows (assumes Visual Studio 2015): +
        build  -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc  -a IA32  -t VS2015x86  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042  -DSHELL_TYPE=BUILD_SHELL  -DMAX_LOGICAL_PROCESSORS=1
+dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd
        -
        • -
    4. In the .config for coreboot, set the following Kconfig values:
        @@ -125,7 +89,6 @@ dir Build\CorebootPayloadPkgIA32\DEBUG_VS2012x86\FV\UEFIPAYLOAD.fd
      • Get the EDK2 sources:
        1. EDK2: git clone https://github.com/tianocore/edk2.git
          2. -
        2. EDK2-FatPkg: git clone https://github.com/tianocore/edk2-FatPkg.git FatPkg
        3. EDK2-non-osi: git clone https://github.com/tianocore/edk2-non-osi.git
        4. Win32 BaseTools: git clone https://github.com/tianocore/edk2-BaseTools-win32.git
        @@ -134,7 +97,7 @@ dir Build\CorebootPayloadPkgIA32\DEBUG_VS2012x86\FV\UEFIPAYLOAD.fd
        • Linux: 
          export WORKSPACE=$PWD
-export PACKAGES_PATH="$PWD/edk2:$PWD/FatPkg:$PWD/edk2-non-osi"
+export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-non-osi"
 cd edk2
 export WORKSPACE=$PWD
 . edksetup.sh
@@ -142,7 +105,7 @@ export WORKSPACE=$PWD
        • Windows: 
          set WORKSPACE=%CD%
-set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi
+set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi
 set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
 cd edk2
 edksetup.bat
@@ -152,32 +115,27 @@ edksetup.bat
    -

    -EDK2 Documentation: -

    - -
    -

    Quark™ FSP

    +

    Quark™ FSP

    -Documentation: +Getting the Quark FSP source: +

    +
      +
    1. Set up an EDK-II Build Environment
      2. +
    2. cd edk2
      3. +
    3. mkdir QuarkFspPkg
      4. +
    4. cd QuarkFspPkg
      5. +
    5. Use git to clone QuarkFspPkg into the QuarkFpsPkg directory (.)
      6. +
    + +

    +Building QuarkFspPkg:

      -
    • Intel® Firmware Support Package External Architecture Specification V1.1
      • +
    • Linux: QuarkFspPkg/BuildFsp.sh -d32
      • +
    • Windows: QuarkFspPkg/BuildFsp.bat -d32
    @@ -216,6 +174,6 @@ Documentation:
    -

    Modified: 29 February 2016

    +

    Modified: 17 May 2016

    - \ No newline at end of file + diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index 0727e7ba20..1e1e88fcb3 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -5,9 +5,9 @@ -

    x86 FSP 1.1 Development

    +

    x86 FSP 1.1 Integration

    - Firmware Support Package (FSP) development requires System-on-a-Chip (SoC) + Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC) and board support. The combined steps are listed here. The development steps for FSP are listed below: @@ -72,6 +72,6 @@

    -

    Modified: 31 January 2016

    +

    Modified: 17 May 2016

    - \ No newline at end of file + diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index 4d508bfa61..cabcbff0c8 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -8,6 +8,7 @@

    Intel® x86 Boards

    @@ -19,6 +20,7 @@ +

    x86 coreboot Development

    + + +

    Payload Development