From ea81928e948a01dde897b90e8e7454a71d9c0788 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Wed, 11 Jul 2018 13:22:34 +0200 Subject: soc/sifive/fu540: Add driver for OTP memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provides minimal functionality to read the SOC s/n from the NeoFuse one time programmable memory. Change-Id: I14b010ad9958931e0a98a76f76090fd7c66f19a0 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/27435 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- Documentation/mainboard/sifive/hifive-unleashed.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md index 62ee82401c..c5c015ddc1 100644 --- a/Documentation/mainboard/sifive/hifive-unleashed.md +++ b/Documentation/mainboard/sifive/hifive-unleashed.md @@ -18,7 +18,7 @@ The following things are still missing from this coreboot port: - Placing the ramstage in DRAM - Starting the U54 cores - FU540 PIN configuration and GPIO access macros -- FU540 OTP driver and serial number read-out +- Provide serial number to payload (e.g. in device tree) - Support for booting Linux on RISC-V -- cgit v1.2.3