From baa3e70084bac00885667b20efde3e69901cda70 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 21 Apr 2015 14:32:36 -0700 Subject: arm64: Align cache maintenance code with libpayload and ARM32 coreboot and libpayload currently use completely different code to perform a full cache flush on ARM64, with even different function names. The libpayload code is closely inspired by the ARM32 version, so for the sake of overall consistency let's sync coreboot to that. Also align a few other cache management details to work the same way as the corresponding ARM32 parts (such as only flushing but not invalidating the data cache after loading a new stage, which may have a small performance benefit). Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/19785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- payloads/libpayload/arch/arm64/cache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'payloads/libpayload/arch') diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 0755c56731..2d42522588 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -119,7 +119,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) void cache_sync_instructions(void) { - dcache_clean_all(); /* includes trailing DSB (in assembly) */ + uint32_t sctlr = raw_read_sctlr_current(); + if (sctlr & SCTLR_C) + dcache_clean_all(); /* includes trailing DSB (assembly) */ + else if (sctlr & SCTLR_I) + dcache_clean_invalidate_all(); icache_invalidate_all(); /* includes leading DSB and trailing ISB */ } -- cgit v1.2.3