From b72b5d95286a2290554399e0803d4ba5e7b87f8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 4 Jul 2019 21:08:17 +0300 Subject: arch/x86: Clean up PIRQ_ROUTE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/Kconfig | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'src/Kconfig') diff --git a/src/Kconfig b/src/Kconfig index 919d257c62..778f1694b6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -543,10 +543,6 @@ config HAVE_OPTION_TABLE file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig. -config PIRQ_ROUTE - bool - default n - config HAVE_SMI_HANDLER bool default n @@ -591,17 +587,6 @@ config HAVE_PIRQ_TABLE Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE. -config MAX_PIRQ_LINKS - int - default 4 - help - This variable specifies the number of PIRQ interrupt links which are - routable. On most chipsets, this is 4, INTA through INTD. Some - chipsets offer more than four links, commonly up to INTH. They may - also have a separate link for ATA or IOAPIC interrupts. When the PIRQ - table specifies links greater than 4, pirq_route_irqs will not - function properly, unless this variable is correctly set. - config COMMON_FADT bool default n -- cgit v1.2.3