From c913a9c076ce91cda20a59d199c8286a6dded0d0 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 3 Sep 2014 13:19:46 -0500 Subject: arm64: add midr_el1 accessor function Provide access to the MIDR_EL1 register to obtain the main id for determining CPU implementer and part/revision information. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and printed the output of this function on ryu. Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326 Signed-off-by: Patrick Georgi Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/216423 Original-Reviewed-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9032 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/arch/arm64/armv8/lib/sysctrl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/arch/arm64/armv8') diff --git a/src/arch/arm64/armv8/lib/sysctrl.c b/src/arch/arm64/armv8/lib/sysctrl.c index deb991f520..2737f56ad2 100644 --- a/src/arch/arm64/armv8/lib/sysctrl.c +++ b/src/arch/arm64/armv8/lib/sysctrl.c @@ -522,6 +522,16 @@ void raw_write_mair_current(uint64_t mair) SWITCH_CASE_WRITE(raw_write_mair,mair); } +/* MIDR */ +uint32_t raw_read_midr_el1(void) +{ + uint32_t midr_el1; + + __asm__ __volatile__("mrs %0, MIDR_EL1\n\t" : "=r" (midr_el1) : : "memory"); + + return midr_el1; +} + /* MPIDR */ uint64_t raw_read_mpidr_el1(void) { -- cgit v1.2.3