From 57afc5e0f2309ba9f7fbd171642f04c6da9d9976 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 5 Mar 2018 09:53:47 +0100 Subject: arch/arm64/armv8/mmu: Add support for 48bit VA The VA space needs to be extended to support 48bit, as on Cavium SoCs the MMIO starts at 1 << 47. The following changes were done to coreboot and libpayload: * Use page table lvl 0 * Increase VA bits to 48 * Enable 256TB in MMU controller * Add additional asserts Tested on Cavium SoC and two ARM64 Chromebooks. Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/24970 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/arch/arm64/include/armv8/arch/mmu.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'src/arch/arm64/include') diff --git a/src/arch/arm64/include/armv8/arch/mmu.h b/src/arch/arm64/include/armv8/arch/mmu.h index a8120736fa..f0e551e52d 100644 --- a/src/arch/arm64/include/armv8/arch/mmu.h +++ b/src/arch/arm64/include/armv8/arch/mmu.h @@ -69,7 +69,7 @@ /* XLAT Table Init Attributes */ #define VA_START 0x0 -#define BITS_PER_VA 33 +#define BITS_PER_VA 48 /* Granule size of 4KB is being used */ #define GRANULE_SIZE_SHIFT 12 #define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) @@ -77,14 +77,12 @@ #define GRANULE_SIZE_MASK ((1 << GRANULE_SIZE_SHIFT) - 1) #define BITS_RESOLVED_PER_LVL (GRANULE_SIZE_SHIFT - 3) +#define L0_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 3) #define L1_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 2) #define L2_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 1) #define L3_ADDR_SHIFT (GRANULE_SIZE_SHIFT + BITS_RESOLVED_PER_LVL * 0) -#if BITS_PER_VA > L1_ADDR_SHIFT + BITS_RESOLVED_PER_LVL - #error "BITS_PER_VA too large (we don't have L0 table support)" -#endif - +#define L0_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT) #define L1_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) #define L2_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) #define L3_ADDR_MASK (((1UL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) @@ -94,6 +92,7 @@ #define L3_XLAT_SIZE (1UL << L3_ADDR_SHIFT) #define L2_XLAT_SIZE (1UL << L2_ADDR_SHIFT) #define L1_XLAT_SIZE (1UL << L1_ADDR_SHIFT) +#define L0_XLAT_SIZE (1UL << L0_ADDR_SHIFT) /* Block indices required for MAIR */ #define BLOCK_INDEX_MEM_DEV_NGNRNE 0 -- cgit v1.2.3