From 1bb68289001f95b49499ac8eb483a7a10e64cc52 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 31 Dec 2009 12:56:53 +0000 Subject: romcc: - Set __PRE_RAM__ define per default - Properly handle ignored (#ifdef'd out) #include lines amd/serengeti_cheetah_fam10: - write ACPI files to $(obj) instead of the top dir (alias $(CURDIR)) tinybootblock: - provide a way to define code that should be added to the bootblock, to map the entire ROM for use by CBFS amd/model_fxx, amd/model_10xxx: - add CONFIG_SSE walkcbfs.S: - eliminate the use of two registers, to make space for romcc to wiggle amd/serengeti_cheetah_fam10: - use the enable_rom framework. not entirely functional yet Boot-tested on emulation/qemu-x86 Build-tested on amd/serengeti_cheetah_fam10 amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/i386/init/bootblock.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) (limited to 'src/arch/i386/init') diff --git a/src/arch/i386/init/bootblock.c b/src/arch/i386/init/bootblock.c index eea0198d00..3cafef58f3 100644 --- a/src/arch/i386/init/bootblock.c +++ b/src/arch/i386/init/bootblock.c @@ -1,24 +1,46 @@ +#if CONFIG_LOGICAL_CPUS && \ + (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) +#include +#else +#define boot_cpu(x) 1 +#endif + +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#else +static void bootblock_northbridge_init(void) { } +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#else +static void bootblock_southbridge_init(void) { } +#endif + static unsigned long findstage(char* target) { unsigned long entry; asm volatile ( "mov $1f, %%esp\n\t" "jmp walkcbfs\n\t" - "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edx", "edi", "ebp", "esp"); + "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); return entry; } -static void call(unsigned long addr) +static void call(unsigned long addr, unsigned long bist) { - asm volatile ("jmp %0\n\t" : : "r" (addr)); + asm volatile ("jmp %0\n\t" : : "r" (addr), "a" (bist)); } -static void main(void) +static void main(unsigned long bist) { + if (boot_cpu()) { + bootblock_northbridge_init(); + bootblock_southbridge_init(); + } const char* target1 = "fallback/romstage"; unsigned long entry; entry = findstage(target1); - if (entry) call(entry); + if (entry) call(entry, bist); asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); } -- cgit v1.2.3