From deaaab25365b093229836d4294b1868093df7c47 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Wed, 21 Jan 2015 01:51:25 +0000 Subject: arch/mips: Fix bug when performing cache operations Each type of cache might have different cache line size. Call the proper get_<*>cache_line function for each cache type. Fixes problem with get_L2cache_line which previously targeted L3 cache line in the config register, instead of L2 cache. TODO: add support for tertiary caches and have cache operations be called per CPU, not per architecture. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; worked as expected; BRANCH=none Change-Id: I7de946cbd6bac716e99fe07cb0deb5aa76c84171 Signed-off-by: Patrick Georgi Original-Commit-Id: 62e2803c6f2a3ad02dc88f50a4ae2ea00487e3f4 Original-Change-Id: I03071f24aacac1805cfd89e4f44b14ed1c1e984e Original-Signed-off-by: Ionela Voinescu Original-Reviewed-on: https://chromium-review.googlesource.com/241853 Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/9731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/mips/include/arch/cache.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/mips/include') diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index 8c7b6f1aeb..907505981b 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -25,7 +25,7 @@ #define get_icache_line() __get_line_size($16, 1, 19, 3) #define get_dcache_line() __get_line_size($16, 1, 10, 3) -#define get_L2cache_line() __get_line_size($16, 2, 20, 4) +#define get_L2cache_line() __get_line_size($16, 2, 4, 4) #define CACHE_TYPE_SHIFT (0) #define CACHE_OP_SHIFT (2) -- cgit v1.2.3