From 99f2f113ec397dd042dcaa23c47123f3def19ebc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 28 Oct 2016 00:25:02 +0200 Subject: riscv: Unify SBI call implementations under arch/riscv/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/17057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Ronald G. Minnich --- src/arch/riscv/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/riscv/Makefile.inc') diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index cf6ce99fb0..1fe8f7c268 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -34,6 +34,7 @@ $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += misc.c @@ -89,7 +90,6 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = -ramstage-y += trap_handler.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c -- cgit v1.2.3