From 042a8336f3eb7c7ed4358a100fae23967346e7a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 16 Feb 2018 13:36:47 +0100 Subject: arch/riscv: Pass the bootrom-provided FDT to the payload MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The RISC-V boot protocol foresees that at every stage boundary (bootrom to boot loader, boot loader -> OS), register a0 contains the Hart ID and a1 contains the physical address of the Flattened Device Tree that the stage shall use. As a first step, pass the bootrom-provided FDT to the payload, unmodified. Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/23797 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/bootblock.S | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/arch/riscv/bootblock.S') diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 43bca907bb..0b5a2b2961 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -25,7 +25,14 @@ .globl _start _start: - + # The boot ROM may pass the following arguments to coreboot: + # a0: the value of mhartid + # a1: a pointer to the flattened devicetree + # + # Preserve only the FDT pointer. We can query mhartid ourselves at any + # time. + # + csrw mscratch, a1 # N.B. This only works on low 4G of the address space # and the stack must be page-aligned. -- cgit v1.2.3