From 26036d9db342ccee13b8dfaab9aefa9956a067f1 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Sat, 7 Jul 2018 13:34:28 +0200 Subject: arch/riscv: Only execute on hart 0 for now Only execute coreboot on hart 0 until synchronisation between hart's is ready. Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/28605 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/bootblock.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/arch/riscv/bootblock.S') diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 81a4455d97..95e1923ce2 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -24,6 +24,12 @@ .global _estack .globl _start _start: + csrr a0, mhartid + li a3, 0 + beq a0, a3, _hart_zero +_hart_loop: + j _hart_loop +_hart_zero: # The boot ROM may pass the following arguments to coreboot: # a0: the value of mhartid -- cgit v1.2.3