From b09e5001f3071e82ccf7ec64c9cf9a4768d660b1 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Wed, 6 Feb 2019 06:48:51 +0100 Subject: riscv: Add initial support for 32bit boards * Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage. This should probably be changed later. TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands: util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/c/31253 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich --- src/arch/riscv/bootblock.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/arch/riscv/bootblock.S') diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index d4b8be7c2a..b0796f9fbc 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -16,6 +16,7 @@ */ #include +#include #include .section ".text._start", "ax", %progbits @@ -44,7 +45,7 @@ _start: slli t1, a0, RISCV_PGSHIFT add t0, t0, t1 li t1, 0xDEADBEEF - sd t1, 0(t0) + STORE t1, 0(t0) li t1, RISCV_PGSIZE - HLS_SIZE add sp, t0, t1 -- cgit v1.2.3