From 21ed107958b3a2525f01875162d5a83a7900d4b4 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Wed, 29 Aug 2018 17:21:19 +0800 Subject: riscv: add entry assembly file for RAMSTAGE RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling needs to be moved to ddr memory. So add a assembly file to do this. Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/28384 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/riscv/include/arch/header.ld | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/arch/riscv/include') diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index 3e078d8b90..4b1104778c 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include + /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_ARCH(riscv) @@ -21,7 +23,7 @@ PHDRS to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK || ENV_RAMSTAGE ENTRY(_start) #else ENTRY(stage_entry) -- cgit v1.2.3