From 3b5351d0444f028ebdb5d06ee51197e516b0c31e Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Sun, 8 Jul 2018 10:01:14 +0800 Subject: riscv: add spin lock support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add spin lock support for riscv. Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/27356 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- src/arch/riscv/include/arch/smp/spinlock.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/include/arch/smp/spinlock.h b/src/arch/riscv/include/arch/smp/spinlock.h index bdf8ec4584..dc561d30a1 100644 --- a/src/arch/riscv/include/arch/smp/spinlock.h +++ b/src/arch/riscv/include/arch/smp/spinlock.h @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2018 HardenedLinux. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -10,3 +12,29 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#ifndef ARCH_SMP_SPINLOCK_H +#define ARCH_SMP_SPINLOCK_H + +#include +#include + +#define barrier() { asm volatile ("fence" ::: "memory"); } + +typedef struct { + volatile atomic_t lock; +} spinlock_t; + +static inline void spinlock_lock(spinlock_t *lock) +{ + while (atomic_swap(&lock->lock, -1)) + ; + barrier(); +} + +static inline void spinlock_unlock(spinlock_t *lock) +{ + barrier(); + atomic_set(&lock->lock, 0); +} + +#endif // ARCH_SMP_SPINLOCK_H -- cgit v1.2.3