From 64d855dbb0d52b2e4486c48cb6161391b9abecb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 29 Sep 2017 01:37:00 +0200 Subject: arch/riscv: Remove supervisor_trap_entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit coreboot only maintains a single trap entry, because it only runs in machine mode. Change-Id: I7324d9c8897d5c4e9d4784e7bc2a055890eab698 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/22595 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/trap_util.S | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 3036f069ab..72a9ae1ced 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -107,15 +107,7 @@ .globl estack .text - .global supervisor_trap_entry -supervisor_trap_entry: - csrw mscratch, sp - # load in the top of the machine stack - la sp, _estack - addi sp,sp,-MENTRY_FRAME_SIZE - save_tf - move a0,sp - jal trap_handler + .global trap_entry trap_entry: csrw mscratch, sp -- cgit v1.2.3