From d9ff75f2cb944d3536f7a502c1c7519843c06618 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Mon, 22 Aug 2016 19:37:15 +0200 Subject: arch/riscv: Delegate exceptions to supervisor mode if appropriate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/16160 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/arch/riscv/virtual_memory.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index bea552de86..98b7edca4e 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -208,4 +208,14 @@ void mstatus_init(void) clear_csr(mip, MIP_MSIP); set_csr(mie, MIP_MSIP); + + /* Configure which exception causes are delegated to supervisor mode */ + set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH) + | (1 << CAUSE_FAULT_FETCH) + | (1 << CAUSE_ILLEGAL_INSTRUCTION) + | (1 << CAUSE_BREAKPOINT) + | (1 << CAUSE_FAULT_LOAD) + | (1 << CAUSE_FAULT_STORE) + | (1 << CAUSE_USER_ECALL) + ); } -- cgit v1.2.3