From 1bc6a79874bc464167ff27319adc16ec87a7206c Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 29 Sep 2015 14:54:25 -0500 Subject: x86: provide common macro for linking early stages In order to support verstage on x86 one needs to link verstage like romstage since it needs all the cache-as-ram goodies. Therefore, provide a macro that one can invoke that provides the necessary recipes for linking that particular stage in such an environment. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I12f4872df09fff6715829de68fc374e230350c2e Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11739 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/arch/x86/assembly_entry.S | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 src/arch/x86/assembly_entry.S (limited to 'src/arch/x86/assembly_entry.S') diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S new file mode 100644 index 0000000000..c23d177052 --- /dev/null +++ b/src/arch/x86/assembly_entry.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include +#include +#include +#if IS_ENABLED(CONFIG_SSE) +#include +#endif + +/* + * The assembly.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include -- cgit v1.2.3