From d4d5e4d3e10da06a83d57a147bd58a733381de18 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Fri, 16 Mar 2012 19:28:15 +0100 Subject: Via Epia-N and C3: Set ioapic delivery type in Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/435 Tested-by: build bot (Jenkins) --- src/arch/x86/lib/ioapic.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'src/arch/x86/lib') diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 81d964cf94..e974d7cce6 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -89,15 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. -#if CONFIG_EPIA_VT8237R_INIT -#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS -#else -#define IOAPIC_INTERRUPTS_ON_FSB -#endif - -#ifdef IOAPIC_INTERRUPTS_ON_FSB +#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB /* * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. @@ -106,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif -#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS +#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif -- cgit v1.2.3