From 8418fd418c8fcef5ca59109be33dececee9cda29 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 22 Apr 2019 16:26:23 -0600 Subject: x86: Introduce RESET_VECTOR_IN_RAM option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create a new Kconfig symbol that allows an x86 device to begin execution when its reset vector is in DRAM and not at the traditional 0xfffffff0. The implementation will follow later, this is just to setup various ENV_xxx definitions correctly for the build environment. Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Signed-off-by: Marshall Dawson Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/memlayout.ld | 18 ++++++++++++------ 2 files changed, 19 insertions(+), 6 deletions(-) (limited to 'src/arch/x86') diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 2ace7f753d..a7d10fb502 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,6 +81,13 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 && SMP +config RESET_VECTOR_IN_RAM + bool + depends on ARCH_X86 + help + Select this option if the x86 soc implements custom code to handle the + reset vector in RAM instead of the traditional 0xfffffff0 location. + # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. config SIPI_VECTOR_IN_ROM diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index cc72552254..1e4ec0df81 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -16,6 +16,15 @@ #include #include +/* Pull in the either CAR or early DRAM rules. */ +#if ENV_ROMSTAGE_OR_BEFORE +#if ENV_CACHE_AS_RAM +#define EARLY_MEMLAYOUT "car.ld" +#else +#error "Early DRAM environment for x86 is work-in-progress. */ +#endif +#endif + SECTIONS { /* @@ -34,23 +43,20 @@ SECTIONS * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_VERSTAGE /* The 1M size is not allocated. It's just for basic size checking. * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK /* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains * the logic for the romcc linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) - /* Pull in the cache-as-ram rules. */ - #include "car.ld" + #include EARLY_MEMLAYOUT #elif ENV_POSTCAR POSTCAR(32M, 1M) -- cgit v1.2.3