From 4d7d25f38abac4bcd3ea88a50b5f529f1e9ddb44 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 25 Jul 2014 14:39:05 -0600 Subject: payloads/external/SeaBIOS: Allow setting buffers below 0xC0000 Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/6364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Edward O'Callaghan --- src/arch/x86/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch') diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 036dc1a7a0..aa058c01eb 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -351,6 +351,7 @@ seabios: CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ + CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo: -- cgit v1.2.3