From 4f42eead361b8d6b2f96031bcaf4627f2a5ea8a6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 5 Mar 2019 16:45:14 +0530 Subject: arch/x86/postcar: Add separate timestamp for postcar stage This patch adds dedicated timestamp value for postcar stage. TEST=Able to see "start of postcar" and "end of postcar" timestamp while executing cbmem -t after booting to chrome console. > cbmem -t 951:returning from FspMemoryInit 20,485,324 (20,103,067) 4:end of romstage 20,559,235 (73,910) 100:start of postcar 20,560,266 (1,031) 101:end of postcar 20,570,038 (9,772) Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/postcar.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch') diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824e6f..b4efc949b4 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include #include #include +#include /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -35,6 +36,8 @@ void main(void) /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); + timestamp_add_now(TS_START_POSTCAR); + display_mtrrs(); /* Load and run ramstage. */ -- cgit v1.2.3